Datasheet

LTC3852
25
3852f
can be computed using the duty cycle (D = V
OUT
/V
IN
).
The effective MOSFET DC resistance is therefore:
R
ON(EFF)
= D • R
ON(TOP)
+ (1-D) • R
ON(BOT)
The effective MOSFET resistance can then be summed
with the DCR of the inductor and the sense resistor
to obtain the overall series resistance. For example,
consider a DC/DC converter with a 3.3V input voltage
and a 1.2V/15A output. The nominal duty cycle of this
converter is 36% (1.2V/3.3V). For a design with R
ON(TOP)
= 8m and R
ON(BOT)
= 2m, the effective MOSFET DC
resistance is (0.36) • 0.008 + (1-0.36) • 0.002 = 4.2m.
For an inductor DCR = 1m and a 2m sense resistor,
the total series resistance is 7.2m. For an output
current range of 5A to 15A, the total I
2
R losses range
from 1% to 9% for a 1.2V output. It is worth noting that
the losses due to the sense resistor at full load (15A)
are 450mW, or 2.5%. If the same application used
a DCR current sensing scheme, the peak effi ciency
would be 2.5% higher, an expensive component would
be eliminated from the bill of materials, and the
solution size would be smaller. The effi ciency varies
as the inverse square of V
OUT
for the same external
components and output power level. The combined
effects of increasingly lower output voltages and higher
currents required by high performance digital systems
is not doubling but quadrupling the importance of loss
terms in the switching regulator system!
2. Since the LTC3852 was optimized for low supply voltage
applications, the transition losses for the top MOSFET
can normally be neglected. Transition losses for the
top MOSFET only become signifi cant when operating
at high input voltages (typically 15V or greater). This
condition can occur, however, when the input to the
charge pump is not the same voltage as the input to the
DC/DC converter power stage. For example, an auxiliary,
low current 3.3V supply could be connected to the input
of the charge pump (V
IN1
), while the DC/DC converter
power stage could draw power from a high current 12V
supply. Transition losses for the upper power MOSFET
can be estimated from the following equation:
Transition Loss = (1.7)V
DS(MAX)
2
• I
O(MAX)
• C
RSS
• f
SW
APPLICATIONS INFORMATION
3. The INTV
CC
current is the sum of the MOSFET driver and
DC bias requirements of the internal circuitry. The gate
drive current results from charging the gate capacitance
of the power MOSFETs. Each time a MOSFET gate is
switched on, a packet of charge Q
G
moves from INTV
CC
to the MOSFET gate. The resulting dQ/dt is a current
into INTV
CC
that is typically much larger than the DC
bias current for the internal control circuitry. In CCM
operation, I
GATE
= f
SW
• (Q
G(TOP)
+ Q
G(BOT)
), where
Q
G(TOP)
and Q
G(BOT)
are the gate charges of the top
and bottom MOSFETs respectively. These parameters
are listed on most power MOSFET datasheets.
4. The DC bias current for the controller is specifi ed in the
Electrical Characteristics table, and is typically 1.2mA.
This current is almost always much smaller than the
gate charge current associated with the power MOSFETs
in CCM operation.
5. In most LTC3852 applications, the output of the charge
pump will be connected to the V
IN2
and INTV
CC
pins of
the controller. The DC bias current into the controller
V
IN2
pin, as well as the gate charge current associated
with the power MOSFETs, will typically be supplied by
the charge pump. Because the charge pump has a fi nite
power effi ciency, the input current will be higher that
the output current when the charge pump is active.
For a 3.3V input application where the output of the
charge pump is 5.1V, this effi ciency is approximately
72%, as shown in the graph in the Typical Performance
Characteristics. As a result, for every 1mA of current
required by the controller, about 1.4mA will be drawn
from the V
IN1
pin.
The DC bias current of the charge pump within the LTC3852
is typically only 60µA. For the purposes of power losses, this
bias current is typically 2 orders of magnitude lower than
the gate drive current, and can therefore be neglected.
Other “hidden” losses such as copper trace and the battery
internal resistance can account for an additional several
percent effi ciency degradation in portable systems. It is
very important to include these “system” level losses
during the design phase. The internal battery and fuse
resistance losses can be minimized by making sure that
C
IN
has adequate charge storage and very low ESR at the
switching frequency. A 25W supply will typically require