Datasheet

LTC3851
22
3851fb
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10F capacitor would
require a 250s rise time, limiting the charging current
to about 200mA.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3851. These items are also illustrated graphically
in the layout diagram of Figure 9. Check the following in
your layout:
1. Are the board signal and power grounds segregated?
The LTC3851 GND pin should tie to the ground plane
close to the input capacitor(s). The low current or signal
ground lines should make a single point tie directly to
the GND pin. The synchronous MOSFET source pins
should connect to the input capacitor(s) ground.
2. Does the V
FB
pin connect directly to the feedback resis-
tors? The resistive divider R1, R2 must be connected
between the (+) plate of C
OUT
and signal ground. The
47pF to 100pF capacitor should be as close as possible
to the LTC3851. Be careful locating the feedback resis-
tors too far away from the LTC3851. The V
FB
line should
not be routed close to any other nodes with high slew
rates.
3. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The fi lter capaci-
tor between SENSE
+
and SENSE
–
should be as close
as possible to the LTC3851. Ensure accurate current
sensing with Kelvin connections as shown in Figure
10. Series resistance can be added to the SENSE lines
to increase noise rejection and to compensate for the
ESL of R
SENSE
.
APPLICATIONS INFORMATION
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
MODE/PLLIN
FREQ/PLLFLTR
RUN
TK/SS
I
TH
V
FB
SENSE
–
SENSE
+
SW
TG
BOOST
V
IN
INTV
CC
BG
GND
I
LIM
LTC3851
47pF
C
C
C
SS
0.1µF
C
C2
R
FREQ
R
C
1000pF
+
C
OUT
R1
R2
C
B
D
B
R
SENSE
M2
4.7µF
M1
+
C
IN
+
–
–
L1
V
IN
+
V
OUT
3851 F09
10
10
+
Figure 9. LTC3851 Layout Diagram