Datasheet

LTC3851-1
19
38511fa
APPLICATIONS INFORMATION
Fault Conditions: Current Limit and Current Foldback
The LTC3851-1 includes current foldback to help limit
load current when the output is shorted to ground. If the
output falls below 40% of its nominal output level, the
maximum sense voltage is progressively lowered from
its maximum programmed value to about 25% of the that
value. Foldback current limiting is disabled during soft-
start or tracking. Under short-circuit conditions with very
low duty cycles, the LTC3851-1 will begin cycle skipping
in order to limit the short-circuit current. In this situation
the bottom MOSFET will be dissipating most of the power
but less than in normal operation. The short-circuit ripple
current is determined by the minimum on-time t
ON(MIN)
of the LTC3851-1 (≈90ns), the input voltage and inductor
value:
∆It
V
L
LSC ONMIN
IN
() ( )
•=
The resulting short-circuit current is:
I
MaxV
R
I
SC
SENSE
SENSE
LSC
=
14
1
2
/
–
()
∆
Programming Switching Frequency
To set the switching frequency of the LTC3851-1, connect
a resistor, R
FREQ
, between FREQ/PLLFLTR and GND. The
relationship between the oscillator frequency and R
FREQ
is shown in Figure 7. A 0.1µF bypass capacitor should be
connected in parallel with R
FREQ
.
Phase-Locked Loop and Frequency Synchronization
The LTC3851-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (V
CO
) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the MODE/PLLIN pin. This phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen tary
current sources that charge or discharge the external fi lter
network connected to the FREQ/PLLFLTR pin. Note that the
LTC3851-1 can only be synchronized to an external clock
whose frequency is within range of the LTC3851-1’s internal
V
CO
.This is guaranteed to be between 250kHz and 750kHz.
A simplifi ed block diagram is shown in Figure 8.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sunk con-
tinuously from the phase detector output, pulling down the
FREQ/PLLFLTR pin. When the external clock frequency is
less than f
OSC
, current is sourced continuously, pulling up
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the fi lter capacitor C
LP
holds the voltage.
Figure 7. Relationship Between Oscillator Frequency
and Resistor Connected Between FREQ/PLLFLTR and GND
Figure 8. Phase-Locked Loop Block Diagram
R
FREQ
(k)
20
250
OSCILLATOR FREQUENCY (kHz)
300
400
450
500
750
600
60
100
120
38511 F07
350
650
700
550
40
80
140
160
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.7V
R
LP
C
LP
38511 F08
FREQ/PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN