Datasheet

LTC3851A
17
3851afa
applicaTions inForMaTion
and the BOOST pin follows. With the topside MOSFET on,
the boost voltage is above the input supply:
V
BOOST
= V
IN
+ V
INTVCC
The value of the boost capacitor C
B
needs to be 100 times
that of the total input capa citance of the topside MOSFET.
The reverse break down of the external Schottky diode
must be greater than V
IN(MAX)
.
Undervoltage Lockout
The LTC3851A has two functions that help protect the
controller in case of undervoltage conditions. A precision
UVLO comparator constantly monitors the INTV
CC
voltage
to ensure that an adequate gate-drive voltage is present.
It locks out the switching action when INTV
CC
is below
3.2V. To prevent oscillation when there is a disturbance
on the INTV
CC
, the UVLO comparator has 400mV of preci-
sion hysteresis.
Another way to detect an undervoltage condition is to
monitor the V
IN
supply. Because the RUN pin has a preci-
sion turn-on reference of 1.22V, one can use a resistor
divider to V
IN
to turn on the IC when V
IN
is high enough.
C
IN
Selection
In continuous mode, the source current of the top N-
channel MOSFET is a square wave of duty cycle V
OUT
/
V
IN
. To prevent large voltage transients, a low ESR input
capacitor sized for the maximum RMS current must be
used. The maximum RMS capacitor current is given by:
I
RMS
≅ I
O(MAX)
V
OUT
V
IN
V
IN
V
OUT
– 1






1/2
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
O(MAX)
/2. This simple worst-case condition is
com monly used for design because even significant
deviations do not offer much relief. Note that capacitor
manufacturers’ ripple current ratings are often based on
only 2000 hours of life. This makes it advisable to further
derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may
also be paralleled to meet size or height requirements in
the design. Always consult the manufacturer if there is
any question.
C
OUT
Selection
The selection of C
OUT
is primarily determined by the effec-
tive series resistance, ESR, to minimize voltage ripple. The
output ripple, ΔV
OUT
, in continuous mode is determined by:
ΔV
OUT
≈ ΔI
L
ESR +
1
8fC
OUT






where f = operating frequency, C
OUT
= output capaci tance
and ΔI
L
= ripple current in the inductor. The output ripple
is highest at maximum input voltage since ΔI
L
increases
with input voltage. Typically, once the ESR require-
ment for C
OUT
has been met, the RMS current rating
generally far exceeds the I
RIPPLE(P-P)
requirement. With
ΔI
L
= 0.3I
OUT(MAX)
and allowing 2/3 of the ripple to be
due to ESR, the output ripple will be less than 50mV at
maximum V
IN
if the I
LIM
pin is configured to float and:
C
OUT
Required ESR < 2.2R
SENSE
C
OUT
>
1
8fR
SENSE
The first condition relates to the ripple current into the ESR
of the output capacitance while the second term guaran tees
that the output capacitance does not significantly discharge
during the operating frequency period due to ripple current.
The choice of using smaller output capaci tance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage at or below 50mV. The I
TH
pin
OPTI-LOOP compensation compo nents can be optimized
to provide stable, high perfor mance transient response
regardless of the output capaci tors selected.
The selection of output capacitors for applications with
large load current transients is primarily determined by the
voltage tolerance specifications of the load. The resistive
component of the capacitor, ESR, multiplied by the load
current change, plus any output voltage ripple must be
within the voltage tolerance of the load.