Datasheet

LTC3850/LTC3850-1
24
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Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of the
losses in LTC3850 circuits: 1) IC V
IN
current, 2) INTV
CC
regulator current, 3) I
2
R losses, 4) Topside MOSFET
transition losses.
1. The V
IN
current is the DC supply current given in
the Electrical Characteristics table, which excludes
MOSFET driver and control currents. V
IN
current typi-
cally results in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from INTV
CC
to ground. The resulting dQ/dt is a cur-
rent out of INTV
CC
that is typically much larger than the
control circuit current. In continuous mode, I
GATECHG
= f(Q
T
+ Q
B
), where Q
T
and Q
B
are the gate charges of
the topside and bottom side MOSFETs.
Supplying INTV
CC
power through EXTV
CC
from an out-
put-derived source will scale the V
IN
current required
for the driver and control circuits by a factor of (Duty
Cycle)/(Efficiency). For example, in a 20V to 5V applica-
tion, 10mA of INTV
CC
current results in approximately
2.5mA of V
IN
current. This reduces the mid-current loss
from 10% or more (if the driver was powered directly
from V
IN
) to only a few percent.
3. I
2
R losses are predicted from the DC resistances of the
fuse (if used), MOSFET, inductor, current sense resistor.
In continuous mode, the average output current flows
through L and R
SENSE
, but is “chopped” between the
topside MOSFET and the synchronous MOSFET. If the
two MOSFETs have approximately the same R
DS(ON)
,
then the resistance of one MOSFET can simply be
summed with the resistances of L and R
SENSE
to obtain
I
2
R losses. For example, if each R
DS(ON)
= 10mΩ, R
L
= 10mΩ, R
SENSE
= 5mΩ, then the total resistance is
25mΩ. This results in losses ranging from 2% to 8%
as the output current increases from 3A to 15A for
a 5V output, or a 3% to 12% loss for a 3.3V output.
Efficiency varies as the inverse square of V
OUT
for the
same external components and output power level. The
combined effects of increasingly lower output voltages
and higher currents required by high performance digital
systems is not doubling but quadrupling the importance
of loss terms in the switching regulator system!
4. Transition losses apply only to the topside MOSFET(s),
and become significant only when operating at high
input voltages (typically 15V or greater). Transition
losses can be estimated from:
Transition Loss = (1.7) V
IN
2
I
O(MAX)
C
RSS
f
Other “hidden” losses such as copper trace and internal
battery resistances can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these “system” level losses during
the design phase. The internal battery and fuse resistance
losses can be minimized by making sure that C
IN
has
adequate charge storage and very low ESR at the switch-
ing frequency. A 25W supply will typically require a
minimum of 20µF to 40µF of capacitance having
a maximum of 20mΩ to 50mΩ of ESR. The LTC3850
2-phase architecture typically halves this input capacitance
requirement over competing solutions. Other losses
including Schottky conduction losses during dead time
and inductor core losses generally account for less than
2% total additional loss.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge or
discharge C
OUT
generating the feedback error signal that
forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recovery
time V
OUT
can be monitored for excessive overshoot or
ringing, which would indicate a stability problem. The
availability of the I
TH
pin not only allows optimization of
control loop behavior but also provides a DC coupled and
AC filtered closed loop response test point. The DC step,
rise time and settling at this test point truly reflects the
closed loop response. Assuming a predominantly second
order system, phase margin and/or damping factor can be
estimated using the percentage of overshoot seen at this
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