Datasheet

LTC3838
44
3838fa
• The path formed by the top and bottom N-channel
MOSFETs, and the C
IN
capacitors should have short
leads and PCB trace. The (–) terminal of output capaci-
tors should be connected close to the (–) terminal of
C
IN
, but away from the loop described above. This is
to achieve an effect of Kevin (4-wire) connection to the
input ground so that the “chopped” switching current
will not flow through the path between the input ground
and the output ground, and cause common mode output
voltage ripple.
• Several smaller sized ceramic output capacitors, C
OUT
,
can be placed close to the sense resistors and before
the rest bulk output capacitors.
• The filter capacitor between the SENSE
+
and SENSE
–
pins
should always be as close as possible to these pins.
Ensure accurate current sensing with Kevin (4-wire)
connections to the soldering pads from underneath
the sense resistors or inductor. A pair of sense traces
should be routed together with minimum spacing.
R
SENSE
, if used, should be connected to the inductor
on the noiseless output side, and its filter resistors
close to the SENSE
+
/SENSE
–
pins. For DCR sensing,
however, filter resistor should be placed close to the
inductor, and away from the SENSE
+
/SENSE
–
pins, as
its terminal is the SW node.
• Keep small-signal components connected noise-sensi-
tive pins (give priority to SENSE
+
/SENSE
–
, V
OUTSENSE1
+
/
V
OUTSENSE1
–
, V
FB2
, RT , ITH, V
RNG
pins) on the left hand
side of the IC as close to their respective pins as pos-
sible. This minimizes the possibility of noise coupling
into these pins. If the LTC3838 can be placed on the
bottom side of a multilayer board, use ground planes
to isolate from the major power components on the top
side of the board, and prevent noise coupling to noise
sensitive components on the bottom side.
• Place the resistor feedback divider R
FB1
, R
FB2
close to
V
OUTSENSE1
+
and V
OUTSENSE1
–
pins for Channel 1, or
V
FB2
pin for Channel 2, so that the feedback voltage
tapped from the resistor divider will not be disturbed by
noise sources. Route remote sense PCB traces (use a
pair of wires closely together for differential sensing in
Channel 1) directly to the terminals of output capacitors
for best output regulation.
• Place decoupling capacitors C
ITH2
next to the ITH and
SGND pins with short, direct trace connections.
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor C
INTVCC
between
the INTV
CC
pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor C
DRVCC
close
to the IC, between the combined DRV
CC1,2
pins and
PGND.
• Filter the V
IN
input to the LTC3838 with an RC filter.
Place the filter capacitor close to the V
IN
pin.
• If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of LTC3838.
Use multiple large vias for power components.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.
PCB Layout Debugging
Only after each controller is checked for its individual
performance should both controllers be turned on at the
same time. It is helpful to use a current probe to monitor
the current in the inductor while testing the circuit. Monitor
the output switching node (SW pin) to synchronize the
oscilloscope to the internal oscillator output CLKOUT, or
external clock if used. Probe the actual output voltage as
well. Check for proper performance over the operating
voltage and current range expected in the application.
The frequency of operation should be maintained over
the input voltage range. The phase should be maintained
APPLICATIONS INFORMATION