Datasheet

LTC3838
42
3838fa
APPLICATIONS INFORMATION
• Keep the switch nodes (SW1,2), top gates (TG1,2) and
boost nodes (BOOST1,2) away from noise-sensitive
small-signal nodes, especially from the opposite
channel’s voltage and current sensing feedback pins.
These nodes have very large and fast moving signals
and therefore should be kept on the “output side” of
the LTC3838 (power-related pins are toward the right
hand side of the IC), and occupy minimum PC trace
area. Use compact switch node (SW) planes to improve
cooling of the MOSFETs and to keep EMI down. If DCR
sensing is used, place the top filter resistor (R1 only in
Figure 5) close to the switch node.
DTR2 RUN2
SENSE2
–
SENSE2
+
V
FB2
TRACK/SS2
ITH2
R
FB2(2)
R
ITH2(2)
C
SS2
C
ITH1(2)
C
ITH2(2)
LOCALIZED
SGND TRACE
PGOOD2
BOOST2
TG2
C
B2
D
B2
D
B1
R
INTVCC
SW2
DRV
CC2
EXTV
CC
V
IN
DRV
CC1
BG1
SW1
TG1
BOOST1
PGOOD1
RUN1
DTR1
PGND
INTV
CC
BG2
C
INTVCC
C
VIN
R
VIN
C
DRVCC
C
B1
C
IN
CERAMIC
CERAMIC
MT2
MB2
MT1
MB1
+
V
IN
L2
L1
C
OUT2
V
OUT2
PGND
V
OUT1
BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH.
+
C
OUT1
+
R
SENSE1
R
SENSE2
RT
R
T
V
RNG2
PHASMD
MODE/PLLIN
CLKOUT
SGND
V
RNG1
R
ITH1(2)
R
FB1(2)
C
ITH2(1)
C
ITH1(1)
C
SS1
R
FB1(1)
R
ITH1(1)
ITH1
TRACK/SS1
V
OUTSENSE1
+
V
OUTSENSE1
–
SENSE1
+
SENSE1
–
R
ITH2(1)
R
FB2(1)
Figure 14. Recommended PCB Layout Diagram