Datasheet

LTC3838
41
3838fa
APPLICATIONS INFORMATION
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select the C
IN
capacitors to give ample capacitance and
RMS ripple current rating. Consider worst-case duty cycles
per Figure 6: If operated at steady-state with SW nodes
fully interleaved, the two channels would generate not
more than 7.5A RMS at full load. In this design example,
3 × 10µF 35V X5R ceramic capacitors are put in parallel
to take the RMS ripple current, with a 220µF aluminum-
electrolytic bulk capacitor for stability. For 10µF 1210 X5R
ceramic capacitors, try to keep the ripple current less
than 3A RMS through each device. The bulk capacitor
is chosen for RMS rating per simulation with the circuit
model provided.
The output capacitor C
OUT
is chosen for a low ESR of
4.5m to minimize output voltage changes due to inductor
ripple current and load steps. The output voltage ripple
is given as:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
• ESR = 5.85A • 4.5m = 26mV
However, a 10A load step will cause an output change of
up to:
∆V
OUT(STEP)
= ∆I
LOAD
• ESR = 10A • 4.5m = 45mV
Optional 2 × 100µF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
The ITH compensation resistor R
ITH
of 40k and a C
ITH
of
220pF are chosen empirically for fast transient response,
and an additional C
ITH2
= 22pF is added directly from
ITH pin to SGND, to roll off the system gain at switching
frequency and attenuate high frequency noise.
To set up the detect transient (DTR) feature, pick resistors
for an equivalent R
ITH
= R
ITH1
//R
ITH2
close to the 40k.
Here, 1% resistors R
ITH1
= 90.9k (low side) and R
ITH2
= 82.5k (high side) are used, which yields an equivalent
R
ITH
of 43.2k, and a DC-bias threshold of 128mV above
one-half of INTV
CC
. Note that even though the accuracy
of the equivalent compensation resistance R
ITH
is not as
important, always use 1% or better resistors for the resis-
tor divider from INTV
CC
to SGND to guarantee the relative
accuracy of this DC-bias threshold. To disable the DTR
feature, simply use a single R
ITH
resistor to SGND, and
tie the DTR pin to INTV
CC
.
PCB Layout Checklist
The printed circuit board layout is illustrated graphically
in Figure 14. Figure 15 illustrates the current waveforms
present in the various branches of 2-phase synchronous
regulators operating in continuous mode. Use the follow-
ing checklist to ensure proper operation of the LTC3838:
• A multilayer printed circuit board with dedicated ground
planes is generally preferred to reduce noise coupling
and improve heat sinking. The ground plane layer
should be immediately next to the routing layer for the
power components, e.g., MOSFETs, inductors, sense
resistors, input and output capacitors etc.
• Keep SGND and PGND separate. Upon finishing the
layout, connect SGND and PGND together with a single
PCB trace underneath the IC from the SGND pin through
the exposed PGND pad to the PGND pin.
• All power train components should be referenced to
PGND; all components connected to noise-sensitive
pins, e.g., ITH, RT
, TRACK/SS and V
RNG
, should return
to the SGND pin. Keep PGND ample, but SGND area
compact. Use a modified “star ground” technique: a low
impedance, large copper area central PCB point on the
same side of the as the input and output capacitors.
• Place power components, such as C
IN
, C
OUT
, MOSFETs,
D
B
and inductors, in one compact area. Use wide but
shortest possible traces for high current paths (e.g.,
V
IN
, V
OUT
, PGND etc.) to this area to minimize copper
loss.