Datasheet

LTC3838
38
3838fa
APPLICATIONS INFORMATION
3. DRV
CC
current. This is the sum of the MOSFET driver
and INTV
CC
control currents. The MOSFET driver cur-
rents result from switching the gate capacitance of the
power MOSFETs. Each time a MOSFET gate is switched
from low to high to low again, a packet of charge dQ
moves from DRV
CC
to ground. The resulting dQ/dt is a
current out of DRV
CC
that is typically much larger than
the controller I
Q
current. In continuous mode,
I
GATECHG
= f • (Qg
(TOP)
+ Qg
(BOT)
),
where Qg
(TOP)
and Qg
(BOT)
are the gate charges of the
top and bottom MOSFETs, respectively.
Supplying DRV
CC
power through EXTV
CC
could save
several percents of efficiency, especially for high V
IN
applications. Connecting EXTV
CC
to an output-derived
source will scale the V
IN
current required for the driver
and controller circuits by a factor of (Duty Cycle)/(Ef-
ficiency). For example, in a 20V to 5V application, 10mA
of DRV
CC
current results in approximately 2.5mA of V
IN
current. This reduces the mid-current loss from 10%
or more (if the driver was powered directly from V
IN
)
to only a few percent.
4. C
IN
loss. The input capacitor filters large square-wave
input current drawn by the regulator into an averaged
DC current from the supply. The capacitor itself has
a zero average DC current, but square-wave-like AC
current flows through it. Therefore the input capacitor
must have a very low ESR to minimize the RMS current
loss on ESR. It must also have sufficient capacitance
to filter out the AC component of the input current to
prevent additional RMS losses in upstream cabling,
fuses or batteries. The LTC3838 2-phase architecture
improves the ESR loss.
“Hidden” copper trace, fuse and battery resistance, even
at DC current, can cause a significant amount of efficiency
degradation, so it is important to consider them during
the design phase. Other losses, which include the C
OUT
ESR loss, bottom MOSFET ’s body diode reverse-recovery
loss, and inductor core loss generally account for less
than 2% additional loss.
Power losses in the switching regulator will reflect as
a higher than ideal duty cycle, or a longer on-time for a
constant frequency. This efficiency accounted on-time
can be calculated as:
t
ON
≈ t
ON(IDEAL)
/Efficiency
When making adjustments to improve efficiency, the input
current is the best indicator of changes in efficiency. If you
make a change and the input current decreases, then the
efficiency has increased.
Design Example
Consider a channel of step-down converter from V
IN
=
4.5V to 26V to V
OUT
= 1.2V, with I
OUT(MAX)
= 15A, and
f = 350kHz (see Figure 13, Channel 1.
The regulated output voltage is determined by:
V
OUT
= 0.6V • 1+
R
FB2
R
FB1
⎛
⎝
⎜
⎞
⎠
⎟
Using a 10k resistor for R
FB1
, R
FB2
is also 10k.
The frequency is programmed by:
R
T
kΩ
[]
=
41550
fkHz
[]
– 2.2 =
41550
350
– 2.2 ≈116.5
Use the nearest 1% resistor standard value of 115k.
The minimum on-time occurs for maximum V
IN
. Using the
t
ON(MIN)
curves in the Typical Performance Characteristics
as references, make sure that the t
ON(MIN)
at maximum V
IN
is greater than that the LTC3838 can achieve, and allow
sufficient margin to account for the extension of effective
on-time at light load due to the dead times (t
D(TG/BG) +
t
D(TG/BG)
in the Electrical Characteristics). The minimum
on-time for this application is:
t
ON(MIN)
=
V
OUT
V
IN(MAX)
•f
=
1.2V
24V • 350kHz
=143ns