Datasheet

LTC3838
37
3838fa
APPLICATIONS INFORMATION
as long as the OV condition is not present. When inductor
current drops to zero and starts to reverse, BG will turn
back on in forced continuous mode (e.g., the MODE/
PLLIN pin tied to INTV
CC
, or an input clock is present),
even if DTR is still below half INTV
CC
. This is to allow the
inductor current to go negative to quickly pull down the
V
OUT
overshoot. Of course, if the MODE/PLLIN pin is set
to discontinuous mode (i.e., tied to SGND), BG will stay
off as inductor current reverse, as it would with the DTR
feature disabled.
Also, if V
OUT
gets higher than the OV window (7.5%
typical), the DTR function is defeated and BG will turn
on regardless. Therefore, in order for the DTR feature
to reduce V
OUT
overshoot effectively,sufficient output
capacitance needs to be used in the application so that
OV is not triggered with the amount of load step desired
to have its overshoot suppressed.
Experimenting with a 0.6V output application (modified
from the design example circuit by setting V
OUT
to 0.6V
and ITH compensation adjusted accordingly) shows this
detect transient feature significantly reduces the overshoot
peak voltage, as well as time to resume regulation during
load release steps (see application examples in Typical
Performance Characteristics).
Note that it is expected that this DTR feature will cause
additional loss on the bottom MOSFET, due to its body
diode conduction. The bottom MOSFET temperature may
be higher with a load of frequent and large load steps. This
is an important design consideration. Experiments on the
demo board shows a 20°C increase when a continuous
100% to 50% load step pulse train with 50% duty cycle
and 100kHz frequency is applied to the output.
If not needed, this DTR feature can be disabled by tying
the DTR pin to INTV
CC
, or simply leave the DTR pin open
so that an internal 2.5µA current source will pull itself up
to INTV
CC
.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percentage efficiency
can be expressed as:
%Efficiency = 100% – (L1% + L2% + L3% + ...)
where L1%, L2%, etc. are the individual losses as a per-
centage of input power. Although all dissipative elements
in the circuit produce power losses, several main sources
usually account for most of the losses in LTC3838 circuits:
1. I
2
R loss. These arise from the DC resistances of the
MOSFETs, inductor, current sense resistor and is the ma-
jority of power loss at high output currents. In continu-
ous mode the average output current flows though the
inductor L, but is chopped between the top and bottom
MOSFETs. If the two MOSFETs have approximately the
same R
DS(ON)
, then the resistance of one MOSFET can
simply be summed with the inductor’s DC resistances
(DCR) and the board traces to obtain the I
2
R loss. For
example, if each R
DS(ON)
= 8m, R
L
= 5m, and R
SENSE
= 2m the loss will range from 15mW to 1.5W as the
output current varies from 1A to 10A. This results in loss
from 0.3% to 3% a 5V output, or 1% to 10% for a 1.5V
output. Efficiency varies as the inverse square of V
OUT
for the same external components and output power
level. The combined effects of lower output voltages
and higher currents load demands greater importance
of this loss term in the switching regulator system.
2. Transition loss. This loss mostly arises from the brief
amount of time the top MOSFET spends in the satura-
tion (Miller) region during switch node transitions. It
depends upon the input voltage, load current, driver
strength and MOSFET capacitance, among other fac-
tors, and can be significant at higher input voltages or
higher switching frequencies.