Datasheet

LTC3838
27
3838fa
APPLICATIONS INFORMATION
C
OUT
Selection
The selection of output capacitance C
OUT
is primarily
determined by the effective series resistance, ESR, to
minimize voltage ripple. The output voltage ripple ∆V
OUT
,
in continuous mode is determined by:
ΔV
OUT
≤ΔI
L
R
ESR
+
1
8•f•C
OUT
⎛
⎝
⎜
⎞
⎠
⎟
where f is operating frequency, and ∆I
L
is ripple current
in the inductor. The output ripple is highest at maximum
input voltage since ∆I
L
increases with input voltage. Typi-
cally, once the ESR requirement for C
OUT
has been met,
the RMS current rating generally far exceeds that required
from ripple current.
In multiphase single-output applications, it is advisable to
consider ripple requirements at specific load conditions.
At steady state, the LTC3838’s individual phases are inter-
leaved, and their ripples cancel each other at the output,
so ripple on C
OUT
is reduced. During transient, when the
phases are not fully interleaved, the ripple cancellation
may not be as effective. While the worst-case ∆I
L
is the
sum of the ∆I
L
s of individual phases aligned during a
fast transient, such ripple tends to counteract the effect
of load transient itself and lasts for only a short time. For
example, during sudden load current increase, the phases
align to ramp up the total inductor current to quickly pull
the V
OUT
up from the droop.
The choice of using smaller output capacitance increases
the ripple voltage due to the discharging term but can be
compensated for by using capacitors of very low ESR to
maintain the ripple voltage.
Multiple capacitors placed in parallel may be needed to
meet the ESR and RMS current handling requirements.
Dry tantalum, special polymer, aluminum electrolytic and
ceramic capacitors are all available in surface mount pack-
ages. Special polymer capacitors offer very low ESR but
have lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long-term reliability.
Ceramic capacitors have excellent low ESR characteristics
but can have a high voltage coefficient and audible piezo-
electric effects. The high Q of ceramic capacitors with trace
inductance can also lead to significant ringing. When used
as input capacitors, care must be taken to ensure that ring-
ing from inrush currents and switching does not pose an
overvoltage hazard to the power switches and controller.
For high switching frequencies, reducing output ripple and
better EMI filtering may require small value capacitors that
have low ESL (and correspondingly higher self-resonant
frequencies) to be placed in parallel with larger value
capacitors that have higher ESL. This will ensure good
noise and EMI filtering in the entire frequency spectrum
of interest. Even though ceramic capacitors generally
have good high frequency performance, small ceramic
capacitors may still have to be parallel connected with
large ones to optimize performance.
High performance through-hole capacitors may also be
used, but an additional ceramic capacitor in parallel is
recommended to reduce the effect of their lead inductance.
Remember also to place high frequency decoupling capaci-
tors as close as possible to the power pins of the load.
Top MOSFET Driver Supply (C
B
, D
B
)
An external bootstrap capacitor, C
B
, connected to the
BOOST pin supplies the gate drive voltage for the topside
MOSFET. This capacitor is charged through diode D
B
from
DRV
CC
when the switch node is low. When the top MOSFET
turns on, the switch node rises to V
IN
and the BOOST pin
rises to approximately V
IN
+ INTV
CC
. The boost capacitor
needs to store approximately 100 times the gate charge
required by the top MOSFET. In most applications a 0.1µF
to 0.47µF, X5R or X7R dielectric capacitor is adequate. It
is recommended that the BOOST capacitor be no larger
than 10% of the DRV
CC
capacitor, C
DRVCC
, to ensure that
the C
DRVCC
can supply the upper MOSFET gate charge