Datasheet

LTC3838
11
3838fa
V
OUTSENSE1
–
(Pin 13/Pin 17): Differential Output Sense
Amplifier (–) Input of Channel 1. Connect this pin to the
negative terminal of the output load capacitor of V
OUT1
.
SENSE1
+
, SENSE2
+
(Pins 14, 37/Pins 18, 3): Differential
Current Sense Comparator (+) Inputs. The ITH pin voltage
and controlled offsets between the SENSE
+
and SENSE
–
pins set the current trip threshold. The comparator can
be used for R
SENSE
sensing or inductor DCR sensing. For
R
SENSE
sensing, Kelvin (4-wire) connect the SENSE
+
pin
to the (+) terminal of R
SENSE
. For DCR sensing, tie the
SENSE
+
pins to the connection between the DCR sense
capacitor and sense resistor tied across the inductor.
SENSE1
–
, SENSE2
–
(Pins 15, 36/Pins 19, 2): Differential
Current Sense Comparator (–) Input. The comparator can
be used for R
SENSE
sensing or inductor DCR sensing.
For R
SENSE
sensing, Kelvin (4-wire) connect the SENSE
–
pin to the (–) terminal of R
SENSE
. For DCR sensing, tie
the SENSE
–
pin to the DCR sense capacitor tied to the
inductor V
OUT
node connection. These pins also func-
tion as output voltage sense pins for the top MOSFET
on-time adjustment. The impedance looking into these
pins is different from the SENSE
+
pins because there
is an additional 500k internal resistor from each of the
SENSE
–
pins to SGND.
DTR1, DTR2 (Pins 16, 35/Pins 20, 1): Detect Load-
Release Transient for Overshoot Reduction. When load
current suddenly drops, if voltage on this DTR pin drops
below half of INTV
CC
, the bottom gate (BG) could turn
off, allowing the inductor current to drop to zero faster,
thus reducing the V
OUT
overshoot. (Refer to Load-Release
Transient Detection in the Applications Information section
for more details.) An internal 2.5A current source pulls
this pin toward INTV
CC
. To disable the DTR feature, simply
tie the DTR pin to INTV
CC
.
RUN1, RUN2 (Pins 17, 34/Pins 21, 38): Run Control
Inputs. An internal proportional-to-absolute-temperature
(PTAT) pull-up current source (~1.2µA at 25°C) is constantly
connected to this pin. Taking both RUN1 and RUN2 pins
below a threshold voltage (~0.8V at 25°C) shuts down all
bias of INTV
CC
and DRV
CC
and places the LTC3838 into
micropower shutdown mode. Allowing either RUN pin to
rise above this threshold would turn on the internal bias
supply and the circuitry for the particular channel. When
a RUN pin rises above 1.2V, its corresponding channel’s
TG and BG drivers are turned on and an additional 5µA
temperature-independent pull-up current is connected
internally to the RUN pin. Either RUN pin can sink up to
50µA, or be forced no higher than 6V.
PGOOD1, PGOOD2 (Pins 18, 33/Pins 22, 37): Power Good
Indicator Outputs. This open-drain logic output is pulled
to ground when the output voltage goes out of a ±7.5%
window around the regulation point, after a 50µs power-
bad-masking delay. Returning to the regulation point, there
is a much shorter delay to power good, and a hysteresis
of around 2% on both sides of the voltage window.
BOOST1, BOOST2 (Pins 19, 32/Pins 23, 36): Boosted
Floating Supplies for Top MOSFET Drivers. The (+) terminal
of the bootstrap capacitor, C
B
, connects to this pin. The
BOOST pins swing by a V
IN
between a diode drop below
DRV
CC
, or (DRV
CC
– V
D
) and (V
IN
+ DRV
CC
– V
D
).
TG1, TG2 (Pins 20, 31/Pins 24, 35): Top Gate Driver
Outputs. The TG pins drive the gates of the top N-channel
power MOSFET with a voltage swing of V
DRVCC
between
SW and BOOST.
PIN FUNCTIONS
(QFN/TSSOP)