Datasheet

LTC3838-1
42
38381f
For more information www.linear.com/3838-1
APPLICATIONS INFORMATION
R
L2
L2
SW1
R
SENSE2
V
OUT2
C
OUT2
V
IN
C
IN
R
IN
R
L1
BOLD LINES INDICATE
HIGH SWITCHING
CURRENT. KEEP LINES
TO A MINIMUM LENGTH.
L1
SW2
38381 F15
R
SENSE1
V
OUT1
C
OUT1
Figure 15. Branch Current Waveforms
• Use sufficient isolation when routing a clock signal into
the MODE/PLLIN pin or out of the CLKOUT pin, so that
the clock does not couple into sensitive pins.
• Place the ceramic decoupling capacitor C
INTVCC
between
the INTV
CC
pin and SGND and as close as possible to
the IC.
• Place the ceramic decoupling capacitor C
DRVCC
close
to the IC, between the combined DRV
CC1,2
pins and
PGND.
• Filter the V
IN
input to the LTC3838-1 with an RC filter.
Place the filter capacitor close to the V
IN
pin.
• If vias have to be used, use immediate vias to connect
components to the SGND and PGND planes of LTC3838
-1.
Use multiple large vias for power components.
• Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. Connect the copper areas to DC rails only,
e.g., PGND.