Datasheet

LTC3838-1
39
38381f
For more information www.linear.com3838-1
Remember to check the maximum possible peak inductor
current, considering the upper spec limit of V
SENSE(MAX)
and the DCR
(MIN)
at lowest operating temperature, as well
as the maximum ∆I
L
, is not going to saturate the inductor
or exceed the rating of power MOSFETs:
I
L(PEAK)
=
V
SENSE(MAX)
(UpperSpecLimit)
DCR
MIN
1+ T
MIN
– 25°C
( )
• 0.4% / °C




+∆I
L(MAX)
For the external N-channel MOSFETs, Renesas
RJK0305DBP (R
DS(ON)
= 13mΩ max, C
MILLER
=
150pF, V
GS
= 4.5V, θ
JA
= 40°C/W, T
J(MAX)
= 150°C)
is chosen for the top MOSFET (main switch). RJK-
0330DBP (R
DS(ON)
= 3.9mΩ max, V
GS
= 4.5V, θ
JA
=
40°C/W, T
J(MAX)
= 150°C) is chosen for the bottom
MOSFET (synchronous switch). The power dissipation
for each
MOSFET can be calculated for V
IN
= 24V and
typical T
J
= 125°C:
P
TOP
=
1.2V
24V






15A
( )
2
13mΩ
( )
1+ 0.4% 125°C– 25°C
( )




+ 24V
( )
2
15A
2






150pF
( )
2.5Ω
5.3V – 3V
+
1.2Ω
3V






350kHz
( )
= 0.54W
P
BOT
=
24V – 1.2V
24V






15A
( )
2
3.9mΩ
( )
1+ 0.4% 125°C– 25°C
( )




= 1.2W
The resulted junction temperatures at an ambient tem-
perature T
A
= 75°C are:
T
J(TOP)
= 75°C + (0.54W)(40°C/W) = 97°C
T
J(BOT)
= 75°C + (1.2W)(40°C/W) = 123°C
These numbers show that careful attention should be paid
to proper heat sinking when operating at higher ambient
temperatures.
Select the C
IN
capacitors to give ample capacitance and
RMS ripple current rating. Consider worst-case duty
cycles per Figure 6: If operated at steady-state with SW
nodes fully interleaved, the two channels would gener-
ate not more than 7.5A
RMS at full load. In this design
example, 3 × 10µF 35V X5R ceramic capacitors are put
in parallel to take the RMS ripple current, with a 220µF
aluminum-electrolytic bulk capacitor for stability. For
10µF 1210 X5R ceramic capacitors, try to keep the ripple
current less than 3A RMS through each device. The bulk
capacitor is chosen for RMS rating per simulation with
the circuit model
provided.
The output capacitor C
OUT
is chosen for a low ESR of
4.5mΩ to minimize output voltage changes due to inductor
ripple current and load steps. The output voltage ripple
is given as:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
• ESR = 5.85A • 4.5mΩ = 26mV
However, a 10A load step will cause an output change
of up to:
∆V
OUT(STEP)
= ∆I
LOAD
• ESR = 10A • 4.5mΩ = 45mV
Optional 2 × 100µF ceramic output capacitors are included
to minimize the effect of ESR and ESL in the output ripple
and to improve load step response.
The ITH compensation resistor R
ITH
of 40k and a C
ITH
of
220pF are chosen empirically for fast transient response,
and an additional C
ITH2
= 22pF is added directly from ITH pin
to SGND, to roll off the system gain at
switching frequency
and attenuate high frequency noise. For less aggressive
transient response but more stability, lower-valued R
ITH
and higher-valued C
ITH
and C
ITH2
can be used (such as
the various combinations used in Figures 16, 17, 18, 19,
20), which typically results in lower bandwidth but more
phase margin.
To set up the detect transient (DTR) feature, pick resis-
tors for an equivalent R
ITH
= R
ITH1
//R
ITH2
close to the
40k chosen. Here, 1% resistors R
ITH1
= 90.9k (low side)
and R
ITH2
= 82.5k (high side) are used, which yields an
equivalent R
ITH
of 43.2k, and a DC-bias threshold of 236mV
typical above one-half of INTV
CC
(including the 2.5µA
pull-up current from the DTR pin, see the Load-Release
Transient Detection section). Note that even though the
accuracy of the
equivalent compensation resistance R
ITH
is not as important, always use 1% or better resistors for
the resistor divider from INTV
CC
to SGND to guarantee the
relative accuracy of this DC-bias threshold. To disable the
DTR feature, simply use a single R
ITH
resistor to SGND,
and tie the DTR pin to INTV
CC
.
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