Datasheet

LTC3838-1
35
38381f
For more information www.linear.com3838-1
APPLICATIONS INFORMATION
Note the internal 2.5µA pull-up current from the DTR pin
will generate an additional offset on top of the resistor
divider itself, making the total difference between the DC
bias voltage on the DTR pin and half INTV
CC
:
V
DTR
– 0.5V
INTVCC
=
R
ITH1
(R
ITH1
+R
ITH2
)
– 0.5






• 5.3V
+ 2.5µA • R
ITH1
// R
ITH2
( )
As illustrated in Figure 12, when load current suddenly
drops, V
OUT
overshoots, and ITH drops quickly. The voltage
on the DTR pin will also drop quickly, since it is coupled
to the ITH pin through a capacitor. If the load transient
is fast enough that the DTR voltage drops below half of
INTV
CC
, a load release event is detected. The bottom gate
(BG) will be turned off
, so that the inductor current flows
through the body diode in the bottom MOSFET. This al-
lows the SW node to drop below PGND by a voltage of
a forward-conducted silicon diode. This creates a more
negative differential voltage (V
SW
– V
OUT
) across the
inductor, allowing the inductor current to drop at a faster
rate to zero, therefore creating less overshoot on V
OUT
.
The DTR comparator output is overridden by reverse
inductor current detection (I
REV
) and overvoltage (OV)
condition. This means BG will be turned off when SENSE
+
is higher than SENSE
–
(i.e., inductor current is posi-
tive), as long as the OV condition is not present. When
inductor current drops to zero and starts to reverse, BG
will turn back on in forced continuous mode (e.g., the
MODE
/PLLIN pin tied to INTV
CC
, or an input clock is
present), even if DTR is still below half INTV
CC
. This is
to allow the inductor current to go negative to quickly
pull down the V
OUT
overshoot. Of course, if the MODE/
PLLIN pin is set to discontinuous mode (i.e., tied to
SGND), BG will stay off as inductor current reverse, as
it would with
the DTR feature disabled.
Also, if V
OUT
gets higher than the OV window (7.5%
typical), the DTR function is defeated and BG will turn
on regardless. Therefore, in order for the DTR feature
to reduce V
OUT
overshoot effectively,sufficient output
capacitance needs to be used in the application so that
OV is not triggered with the amount of load step desired
to have its overshoot suppressed.
Experimenting
with a 0.6V output application (modified
from the design example circuit by setting V
OUT
to 0.6V
and ITH compensation adjusted accordingly) shows this
detect transient feature significantly reduces the overshoot
peak voltage, as well as time to resume regulation during
load release steps (see application examples in Typical
Performance Characteristics).
Note that it is expected that this DTR feature will cause
additional loss on the bottom MOSFET
, due to its body
diode conduction. The bottom MOSFET temperature may
be higher with a load of frequent and large load steps. This
is an important design consideration. Experiments on the
demo board show a 20°C increase when a continuous
100% to 50% load step pulse train with 50% duty cycle
and 100kHz frequency is applied to the output.
Figure 12. Comparison of V
OUT
Overshoot with Detect Transient (DTR) Feature Enabled and Disabled
(12a) DTR Enabled
38381 F12
(12b) DTR Disabled
BG
5V/DIV
DTR
1V/DIV
I
L
10A/DIV
DTR DETECTS LOAD
RELEASE, TURNS OFF BG
FOR FASTER INDUCTOR
CURRENT (I
L
) DECAY
5µs/DIV
LOAD RELEASE = 15A TO 0A
V
IN
= 5V
V
OUT
= 0.6V
BG TURNS BACK ON, INDUCTOR
CURRENT (I
L
) GOES NEGATIVE
SW
5V/DIV
SW
5V/DIV
BG
5V/DIV
ITH
1V/DIV
I
L
10A/DIV
5µs/DIV
LOAD RELEASE = 15A TO 0A
V
IN
= 5V
V
OUT
= 0.6V
BG REMAINS ON
DURING THE LOAD
RELEASE EVENT