Datasheet

LTC3838-1
31
38381f
For more information www.linear.com3838-1
APPLICATIONS INFORMATION
Minimum On-Time, Minimum Off-Time
and Dropout Operation
The minimum on-time is the smallest duration that LTC3838-
1’s TG (top gate) pin can be in high or “on” state. It has
dependency on the operating conditions of the switching
regulator, and is a function of voltages on the V
IN
and
V
OUT
pins, as well as the value of external resistor R
T
. As
shown by the t
ON(MIN)
curves in the Typical Performance
Characteristics section, a minimum on-time of 30ns can
be achieved when V
OUT
, sensed by the SENSE
–
pin, is at
its minimum regulated value of 0.6V or lower, while V
IN
is
tied to its maximum value of 38V. For larger values of V
OUT
,
smaller values of V
IN
, and/or larger value of R
T
(i.e., lower f),
the minimum achievable on-time will be longer. The valley
mode control architecture allows low on-time, making the
LTC3838-1 suitable for high step-down ratio applications.
The effective on-time, as determined by the SW node
pulse width, can be different from this TG on-time, as it
also depends on external components, as well as loading
conditions of the
switching regulator. One of the factors that
contributes to this discrepancy is the characteristics of the
power MOSFETs. For example, if the top power MOSFET’s
turn-on delay is much smaller than the turn-off delay,
the effective on-time will be longer than the TG on-time,
limiting the effective minimum on-time to a larger value.
Light-load operation, in forced continuous mode, will
further elongate the effective on-time due to the dead
times between the “on” states of TG and BG, as shown in
Figure 11. During the dead time from BG turn-off to TG
turn-on, the inductor current flows in the reverse direction,
charging the SW node high before the TG actually turns
on. The reverse current is typically small, causing a slow
rising edge. On the
falling edge, after the top FET turns off
and before the bottom FET turns on, the SW node lingers
high for a longer duration due to a smaller peak inductor
current available in light load to pull the SW node low. As
a result of the sluggish SW node rising and falling edges,
the effective on-time is extended and not fully controlled
by the TG on
-time. Closer to minimum on-time, this may
cause some phase jitter to appear at light load. As load
current increase, the edges become sharper, and the phase
locking behavior improves.
In continuous mode operation, the minimum on-time limit
imposes a minimum duty cycle of:
D
MIN
= f • t
ON(MIN)
where t
ON(MIN)
is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint. If the minimum on-time that LTC3838-1 can
provide is longer than the on-time required by the duty
cycle to maintain the switching frequency, the switching
frequency will have to decrease to
maintain the duty cycle,
but the output voltage will still remain in regulation. This is
generally more preferable to skipping cycles and causing
larger ripple at the output, which is typically seen in fixed
frequency switching regulators.
Figure 10. Phase and Frequency Locking Behavior During Transient Conditions
PHASE AND
FREQUENCY
LOCK LOST
DUE TO FAST
LOAD STEP
FREQUENCY
RESTORED
QUICKLY
PHASE AND
FREQUENCY
LOCK LOST
DUE TO FAST
LOAD STEP
FREQUENCY
RESTORED
QUICKLY
PHASE LOCK
RESUMED
38381 F10
PHASE AND
FREQUENCY
LOCKED
I
LOAD
CLOCK
INPUT
SW
V
OUT