LTC3838-1 Dual, Fast, Accurate Step-Down DC/DC Controller with Dual Differential Output Sensing DESCRIPTION FEATURES n n n n n n n n n n n n n n Wide VIN Range: 4.5V to 38V, VOUT: 0.6V to 5.5V Two Independent Channels: Dual/Single Output Output Voltage Regulation Accuracy: ±0.67% (VOUT1) and ±0.
LTC3838-1 BOOST2 PGOOD2 RUN2 DTR2 SENSE2– SENSE2+ TOP VIEW VDFB2– 38 37 36 35 34 33 32 VDFB2+ 1 31 TG2 VRNG 2 30 SW2 ITH2 3 29 BG2 TRACK/SS2 4 28 DRVCC2 27 EXTVCC MODE/PLLIN 5 CLKOUT 6 26 INTVCC 39 PGND SGND 7 25 PGND 24 VIN RT 8 23 DRVCC1 PHASMD 9 ITH1 10 22 BG1 TRACK/SS1 11 21 SW1 VOUTSENSE1+ 12 20 TG1 BOOST1 PGOOD1 DTR1 RUN1 13 14 15 16 17 18 19 SENSE1– VIN Voltage.................................................. –0.3V to 40V BOOST1, BOOST2 Voltages......................
LTC3838-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS 4.5 38 V VOUT1 Regulated Differentially with Respect to VOUTSENSE1–, VOUT2 Regulated Differentially with Respect to VDFB2– 0.6 5.
LTC3838-1 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 15V unless otherwise noted (Note 3). SYMBOL PARAMETER CONDITIONS MIN TYP MAX 1.1 1.2 1.3 UNITS Start-Up and Shutdown VRUN1,2 IRUN1,2 RUN Pin On Threshold VRUN1,2 Rising RUN Pin On Hysteresis VRUN1,2 Falling from On Threshold 100 mV RUN Pin Pull-Up Current When Off RUN1,2 = SGND 1.
LTC3838-1 ELECTRICAL CHARACTERISTICS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The junction temperature (TJ, in °C) is calculated from the ambient temperature (TA, in °C) and power dissipation (PD, in Watts) according to the formula: TJ = TA + (PD • θJA) where θJA (in °C/W) is the package thermal impedance.
LTC3838-1 TYPICAL PERFORMANCE CHARACTERISTICS Transient Response (Forced Continuous Mode) Load Step (Forced Continuous Mode) Load Release (Forced Continuous Mode) ILOAD 10A/DIV ILOAD 10A/DIV ILOAD 10A/DIV VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IL 10A/DIV IL 10A/DIV 50µs/DIV LOAD TRANSIENT = 0A TO 15A TO 0A VIN = 12V VOUT = 1.2V FIGURE 17 CIRCUIT, CHANNEL 1 IL 10A/DIV 5µs/DIV LOAD STEP = 0A TO 15A VIN = 12V VOUT = 1.
LTC3838-1 TYPICAL PERFORMANCE CHARACTERISTICS Soft Start-Up Into Prebiased Output Regular Soft Start-Up RUN1 5V/DIV RUN1 5V/DIV TRACK/SS1 200mV/DIV VOUT 500mV/DIV TRACK/SS1 200mV/DIV CSS = 10nF 1ms/DIV VIN = 12V VOUT = 1.2V FORCED CONTINUOUS MODE FIGURE 17 CIRCUIT, CHANNEL 1 38381 G09 CSS = 10nF 1ms/DIV VIN = 12V VOUT = 1.2V VOUT PRE-BIASED TO 0.
LTC3838-1 TYPICAL PERFORMANCE CHARACTERISTICS Output Regulation vs Input Voltage 0.2 0.1 0 –0.1 Output Regulation vs Temperature 0.6 VIN = 15V VOUT = 0.6V VOUT NORMALIZED AT ILOAD = 4A 0.1 NORMALIZED ∆VOUT (%) VOUT = 0.6V ILOAD = 5A VOUT NORMALIZED AT VIN = 15V NORMALIZED ∆VOUT (%) NORMALIZED ∆VOUT (%) 0.2 Output Regulation vs Load Current 0 VIN = 15V VOUT = 0.6V 0.4 ILOAD = 0A VOUT NORMALIZED AT TA = 25°C 0.2 0 –0.2 –0.1 –0.4 –0.2 0 5 10 15 20 25 VIN (V) 30 35 –0.
LTC3838-1 TYPICAL PERFORMANCE CHARACTERISTICS 80 60 40 20 0 –20 VRNG = INTVCC VRNG = SGND –40 –60 0 0.8 1.2 1.6 ITH VOLTAGE (V) 0.4 2.4 2 100 80 VRNG = INTVCC 60 40 VRNG = SGND 20 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) RUN Pin Thresholds vs Temperature SWITCHING REGION STAND-BY REGION 0.8 0.6 SHUTDOWN REGION 3 RUN PIN BELOW 1.2V SWITCHING THRESHOLD 1.05 1.00 0.95 0.90 0 0.
LTC3838-1 PIN FUNCTIONS VDFB2+ (Pin 1): Differential Feedback Amplifier (+) Input of Channel 2. As shown in the Functional Diagram, connect this pin to a 3-resistor feedback divider network, which is composed of RDFB1 and RDFB2 from this pin to the negative and positive terminals of VOUT2 respectively, and a third resistor from this pin to local SGND. The third resistor must have a value equal to RDFB1//RDFB2 for accurate differential regulation.
LTC3838-1 PIN FUNCTIONS VOUTSENSE1– (Pin 13): Differential Output Sense Amplifier (–) Input of Channel 1. Connect this pin to the negative terminal of the output load capacitor of VOUT1. SENSE1+, SENSE2+ (Pin 14, Pin 37): Differential Current Sense Comparator (+) Inputs. The ITH pin voltage and controlled offsets between the SENSE+ and SENSE– pins set the current trip threshold. The comparator can be used for RSENSE sensing or inductor DCR sensing.
LTC3838-1 PIN FUNCTIONS SW1, SW2 (Pin 21, Pin 30): Switch Node Connection to Inductors. Voltage swings are from a diode voltage below ground to VIN. The (–) terminal of the bootstrap capacitor, CB, connects to this node. BG1, BG2 (Pin 22, Pin 29): Bottom Gate Driver Outputs. The BG pins drive the gates of the bottom N‑channel power MOSFET between PGND and DRVCC. DRVCC1, DRVCC2 (Pin 23, Pin 28): Supplies of Bottom Gate Drivers. DRVCC1 is also the output of an internal 5.3V regulator.
LTC3838-1 FUNCTIONAL DIAGRAM VIN VIN IN EN LDO OUT SD 1-2µA PTAT 5µA + UVLO RUN BOOST TG DRV – + 1.2V 4.2V MT L SW EN_DRV – CB DB TG RSENSE VOUT+ DRVCC ~0.8V – – LOGIC CONTROL SENSE– ONE-SHOT TIMER 250k COUT DRVCC1 STOP CDRVCC BG DRV BG MB PGND VOUT– IREV ICMP RT CINTVCC PHASE DETECTOR MODE/CLK DETECT CLOCK PLL/ GENERATOR INTVCC DRVCC2 ON-TIME ADJUST MODE/PLLIN RT ~4.
LTC3838-1 OPERATION (Refer to Functional Diagram) Main Control Loop The LTC3838-1 is a controlled on-time, valley current mode step-down DC/DC dual controller with two channels operating out of phase. Each channel drives both main and synchronous N-channel MOSFETs. The two channels can be either configured to two independently regulated outputs, or combined into a single output. The top MOSFET is turned on for a time interval determined by a one-shot timer.
LTC3838-1 OPERATION (Refer to Functional Diagram) DRVCC/EXTVCC/INTVCC Power DRVCC1,2 are the power for the bottom MOSFET drivers. Normally the two DRVCC pins are shorted together on the PCB, and decoupled to PGND with a minimum 4.7µF ceramic capacitor, CDRVCC. The top MOSFET drivers are biased from the floating bootstrap capacitors (CB1,2) which are recharged during each cycle through an external Schottky diode when the top MOSFET turns off and the SW pin swings down.
LTC3838-1 OPERATION (Refer to Functional Diagram) TRACK/SS is pulled low internally when the corresponding channel’s RUN pin is pulled below the 1.2V threshold (hysteresis applies), or when INTVCC or either of the DRVCC1,2 pins drop below their respective undervoltage lockout (UVLO) thresholds. Light Load Current Operation If the MODE/PLLIN pin is tied to INTVCC or an external clock is applied to MODE/PLLIN, the LTC3838-1 will be forced to operate in continuous mode.
LTC3838-1 OPERATION (Refer to Functional Diagram) “high” and no greater than 0.5V for “low”. The MODE/ PLLIN pin has an internal 600k pull-down resistor. Multichip Operations The PHASMD pin determines the relative phases between the internal reference clock signals for the two channels as well as the CLKOUT signal, as shown in Table 2. The phases tabulated are relative to zero degree (0°) being defined as the rising edge of the internal reference clock signal of channel 1.
LTC3838-1 APPLICATIONS INFORMATION Once the required output voltage and operating frequency have been determined, external component selection is driven by load requirement, and begins with the selection of inductors and current sense method (either sense resistors RSENSE or inductor DCR sensing). Next, power MOSFETs are selected. Finally, input and output capacitors are selected.
LTC3838-1 APPLICATIONS INFORMATION CIN MT LTC3838-1 VOUTSENSE1+ VOUTSENSE1– RFB2 + – VIN POWER TRACE PARASITICS L ±VDROP(PWR) MB COUT RFB1 ILOAD ILOAD GROUND TRACE PARASITICS ±VDROP(GND) OTHER CURRENTS FLOWING IN SHARED GROUND PLANE 38381 F02 Figure 2.
LTC3838-1 APPLICATIONS INFORMATION The inductor value has a direct effect on ripple current. The inductor ripple current ∆IL decreases with higher inductance or frequency and increases with higher VIN: V V ∆IL = OUT 1– OUT f • L VIN Accepting larger values of ∆IL allows the use of low inductances, but results in higher output voltage ripple, higher ESR losses in the output capacitor, and greater core losses. A reasonable starting point for setting ripple current is ∆IL = 0.4 • IMAX.
LTC3838-1 APPLICATIONS INFORMATION RSENSE method offers more precise control of the current limit but the resistor will dissipate loss. The DCR method saves the cost of the sense resistors and may offer better efficiency, especially in high current applications, but tolerance and the variation over temperature in the DCR value usually requires larger design margins.
LTC3838-1 APPLICATIONS INFORMATION the top switch, the value of the parasitic inductance was determined to be 0.5nH using the equation: ESL = VESL(STEP) tON • tOFF • ∆IL tON + tOFF where VESL(STEP) is the voltage step caused by the ESL and shown in Figure 4a, and tON and tOFF are top MOSFET on-time and off-time respectively. If the RC time constant is chosen to be close to the parasitic inductance divided by the sense resistor (L/R), the resulting waveform looks resistive again, as shown in Figure 4b.
LTC3838-1 APPLICATIONS INFORMATION INDUCTOR L DCR VOUT COUT L/DCR = (R1||R2) C1 LTC3838-1 R1 SENSE+ C1 SENSE – R2 (OPT) 38381 F05 If VSENSE(MAX) is within the maximum sense voltage (30mV or 60mV typical) of the LTC3838-1 as set by the VRNG pin, then the RC filter only needs R1. If VSENSE(MAX) is higher, then R2 may be used to scale down the maximum sense voltage so that it falls within range.
LTC3838-1 APPLICATIONS INFORMATION (or the parameter QGD if specified on a manufacturer’s data sheet), divided by the specified VDS test voltage: CMILLER ≅ QGD CIN Selection VDS(TEST) When the IC is operating in continuous mode, the duty cycles for the top and bottom MOSFETs are given by: DTOP = VOUT VIN DBOT = 1– VOUT VIN The MOSFET power dissipations at maximum output current are given by: PTOP = DTOP •IOUT(MAX)2 where TJ is estimated junction temperature of the MOSFET and TA is ambient temperatu
LTC3838-1 APPLICATIONS INFORMATION VIN + ESR(CERAMIC) ESL(BULK) ESL(CERAMIC) CIN(BULK) IPULSE(PHASE1) IPULSE(PHASE2) CIN(CERAMIC) 38381 F06 Figure 6. Circuit Model for Input Capacitor Ripple Current Simulation For simulations with this model, look at the ripple current during steady-state for the case where one phase is fully loaded and the other was not loaded.
LTC3838-1 APPLICATIONS INFORMATION rarely be at 100% of IOUT(MAX). Using the worst-case load current should already have margin built in for transient conditions. The VIN sources of the top MOSFETs should be placed close to each other and share common CIN(s). Separating the sources and CIN may produce undesirable voltage and current resonances at VIN. A small (0.1µF to 1µF) bypass capacitor between the IC’s VIN pin and ground, placed close to the IC, is suggested. A 2.
LTC3838-1 APPLICATIONS INFORMATION turns on, the switch node rises to VIN and the BOOST pin rises to approximately VIN + INTVCC. The boost capacitor needs to store approximately 100 times the gate charge required by the top MOSFET. In most applications a 0.1µF to 0.47µF, X5R or X7R dielectric capacitor is adequate.
LTC3838-1 APPLICATIONS INFORMATION For applications where the main input power never exceeds 5.3V, tie the DRVCC1 and DRVCC2 pins to the VIN input through a small resistor, (such as 1Ω to 2Ω) as shown in Figure 8 to minimize the voltage drop caused by the gate charge current. This will override the LDO and will prevent DRVCC from dropping too low due to the dropout voltage. Make sure the DRVCC voltage exceeds the RDS(ON) test voltage for the external MOSFET which is typically at 4.
LTC3838-1 APPLICATIONS INFORMATION When one particular channel is configured to track an external supply, a voltage divider can be used from the external supply to the TRACK/SS pin to scale the ramp rate appropriately. Two common implementations are coincidental tracking and ratiometric tracking. For coincident tracking, make the divider ratio from the external supply the same as the divider ratio for the differential feedback voltage.
LTC3838-1 APPLICATIONS INFORMATION Phase and Frequency Synchronization For applications that require better control of EMI and switching noise or have special synchronization needs, the LTC3838-1 can synchronize the turn-on of the top MOSFET to an external clock signal applied to the MODE/ PLLIN pin. The applied clock signal needs to be within ±30% of the RT programmed frequency to ensure proper frequency and phase lock. The clock signal levels should generally comply to VPLLIN(H) > 2V and VPLLIN(L) < 0.5V.
LTC3838-1 APPLICATIONS INFORMATION ILOAD CLOCK INPUT PHASE AND FREQUENCY LOCKED PHASE AND FREQUENCY LOCK LOST DUE TO FAST LOAD STEP FREQUENCY RESTORED QUICKLY PHASE LOCK RESUMED PHASE AND FREQUENCY LOCK LOST DUE TO FAST LOAD STEP FREQUENCY RESTORED QUICKLY SW VOUT 38381 F10 Figure 10.
LTC3838-1 APPLICATIONS INFORMATION TG-SW (VGS OF TOP MOSFET) the dead-time delays from TG off to BG on and from BG off to TG on. The minimum off-time that the LTC3838-1 can achieve is 90ns.
LTC3838-1 APPLICATIONS INFORMATION by the voltage on the VRNG pin. With valley current mode control, the maximum sense voltage and the sense resistance determine the maximum allowed inductor valley current. The corresponding output current limit is: ILIMIT = VSENSE(MAX) RSENSE 1 + • ∆IL 2 The current limit value should be checked to ensure that ILIMIT(MIN) > IOUT(MAX).
LTC3838-1 APPLICATIONS INFORMATION related to the stability of the closed-loop system. However, it is better to look at the filtered and compensated feedback loop response at the ITH pin. The gain of the loop increases with the RITH and the bandwidth of the loop increases with decreasing CITH1. If RITH is increased by the same factor that CITH1 is decreased, the zero frequency will be kept the same, thereby keeping the phase the same in the most critical frequency range of the feedback loop.
LTC3838-1 APPLICATIONS INFORMATION Note the internal 2.5µA pull-up current from the DTR pin will generate an additional offset on top of the resistor divider itself, making the total difference between the DC bias voltage on the DTR pin and half INTVCC: RITH1 VDTR – 0.5VINTVCC = – 0.5 • 5.3V (RITH1+RITH2) + 2.5µA • (RITH1 // RITH2 ) As illustrated in Figure 12, when load current suddenly drops, VOUT overshoots, and ITH drops quickly.
LTC3838-1 APPLICATIONS INFORMATION If not needed, this DTR feature can be disabled by tying the DTR pin to INTVCC, or simply leave the DTR pin open so that an internal 2.5µA current source will pull itself up to INTVCC. Efficiency Considerations The percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement.
LTC3838-1 APPLICATIONS INFORMATION constant frequency. This efficiency accounted on-time can be calculated as: tON ≈ tON(IDEAL)/Efficiency When making adjustments to improve efficiency, the input current is the best indicator of changes in efficiency. If you make a change and the input current decreases, then the efficiency has increased. Design Example Consider a channel of step-down converter from VIN = 4.5V to 26V to VOUT = 1.2V, with IOUT(MAX) = 15A, and f = 350kHz (see Figure 13, channel 1).
LTC3838-1 APPLICATIONS INFORMATION + CIN1 220µF CIN2 10µF ×3 2.2Ω 1µF VIN 0.1µF 3.57k VOUT1 1.2V 15A + COUT2 330µF ×2 SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 0.1µF TG1 MT1 4.7µF DRVCC1 INTVCC DRVCC2 EXTVCC BG1 MB1 BG2 VOUTSENSE1+ PGOOD1 0.01µF 220pF 82.5k 115k ITH1 DTR1 VRNG RT SGND RUN1 FORCED CONTINUOUS MODE DISCONTINUOUS MODE EFFICIENCY (%) 40 1.0 VIN = 12V VOUT = 1.2V 0.1 1 LOAD CURRENT (A) 10 220pF 90.9k 82.5k DTR2 38381 F13a PHASMD MODE/PLLIN CLKOUT RUN2 3.
LTC3838-1 APPLICATIONS INFORMATION Remember to check the maximum possible peak inductor current, considering the upper spec limit of VSENSE(MAX) and the DCR(MIN) at lowest operating temperature, as well as the maximum ∆IL, is not going to saturate the inductor or exceed the rating of power MOSFETs: aluminum-electrolytic bulk capacitor for stability. For 10µF 1210 X5R ceramic capacitors, try to keep the ripple current less than 3A RMS through each device.
LTC3838-1 APPLICATIONS INFORMATION PCB Layout Checklist The printed circuit board layout is illustrated graphically in Figure 14. Figure 15 illustrates the current waveforms present in the various branches of 2-phase synchronous regulators operating in continuous mode. Use the following checklist to ensure proper operation: • A multilayer printed circuit board with dedicated ground planes is generally preferred to reduce noise coupling and improve heat sinking.
LTC3838-1 APPLICATIONS INFORMATION RDFB1 RDFB2 RDFB1//RDFB2 RITH2(2) CITH1(2) RITH1(2) VDFB2– SENSE2+ SENSE2– DTR2 RUN2 PGOOD2 BOOST2 VDFB2+ VRNG ITH2 CITH2(2) TG2 SW2 BG2 LTC3838-1 RINTVCC CERAMIC PGND CVIN VIN VIN PHASMD CDRVCC RVIN + PGND CIN CERAMIC + RT COUT1 DRVCC1 RITH1(1) RITH2(1) MB2 + CITH2(1) VOUT2 COUT2 MODE/PLLIN CLKOUT SGND RT MT2 RSENSE2 CINTVCC TRACK/SS2 LOCALIZED SGND TRACE L2 DB2 DRVCC2 EXTVCC INTVCC CSS2 CB2 DB1 ITH1 CITH1(1) TRACK/SS1 RFB2(1) CSS1 R
LTC3838-1 APPLICATIONS INFORMATION SW2 L2 RSENSE2 VOUT2 COUT2 RL2 VIN RIN CIN SW1 L1 RSENSE1 VOUT1 COUT1 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. RL1 38381 F15 Figure 15. Branch Current Waveforms • Use sufficient isolation when routing a clock signal into the MODE/PLLIN pin or out of the CLKOUT pin, so that the clock does not couple into sensitive pins.
LTC3838-1 APPLICATIONS INFORMATION PCB Layout Debugging Only after each controller is checked for its individual performance should both controllers be turned on at the same time. It is helpful to use a current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator output CLKOUT, or external clock if used. Probe the actual output voltage as well.
LTC3838-1 TYPICAL APPLICATIONS + CIN1 100µF CIN2 10µF ×3 2.2Ω 1µF VIN 0.1µF 3.57k VOUT1 1.2V 15A + COUT2 330µF ×2 SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 0.1µF TG1 MT1 4.7µF DRVCC1 INTVCC DRVCC2 EXTVCC BG1 MB1 100k BG2 VOUTSENSE1+ 0.01µF 220pF 115k ITH1 DTR1 VRNG RT SGND RUN1 ITH2 0.01µF 70 POWER LOSS 60 1.0 0.5 50 VIN = 12V VOUT = 1.2V 0.
LTC3838-1 TYPICAL APPLICATIONS + CIN1 220µF CIN2 10µF ×3 2.2Ω 1µF VIN 100Ω L1 0.47µH MT1 + COUT2 330µF ×2 SENSE1+ SENSE2+ BOOST1 BOOST2 TG1 100Ω MT2 TG2 DB2 SW1 4.7µF 1µF MB1 DRVCC1 INTVCC DRVCC2 EXTVCC VOUTSENSE1+ 100k PGOOD1 0.01µF PGOOD1 VDFB2– PGOOD2 ITH1 220pF 115k DTR1 VRNG RT SGND RUN1 ITH2 100k PGOOD2 0.01µF 22pF 220pF 30.
LTC3838-1 TYPICAL APPLICATIONS + CIN2 22µF ×4 CIN1 180µF 2.2Ω 1µF VIN 100Ω L1 0.47µH M1 + SENSE1+ SENSE2+ BOOST1 BOOST2 TG1 COUT2 330µF ×2 0.1µF M2 DB2 SW1 4.7µF 1µF DRVCC1 INTVCC DRVCC2 EXTVCC 0.01µF VOUTSENSE1– VDFB2– PGOOD2 470pF 137k ITH1 DTR1 VRNG RT SGND RUN1 0.01µF 470pF 38381 F18 PHASMD MODE/PLLIN CLKOUT RUN2 80 2 1 10 VIN = 5V FCM VIN = 5V DCM 8 6 80 4 70 2 LOSS 60 0.1 VIN = 12V VOUT = 12V 1 10 LOAD CURRENT (A) 0 100 38381 F18b 60 0.
LTC3838-1 TYPICAL APPLICATIONS 5V TO 5.5V EXTERNAL VIN 3.3V TO 14V + CIN1 180µF CIN2 22µF ×4 2.2Ω 1µF VIN 100Ω L1 0.47µH M1 + SENSE1+ SENSE2+ BOOST1 BOOST2 TG1 100Ω COUT2 330µF ×2 M2 TG2 DB2 SW1 4.7µF 1µF DRVCC1 INTVCC DRVCC2 EXTVCC VOUTSENSE1+ 0.01µF VOUTSENSE1– VDFB2– PGOOD2 470pF 137k ITH1 DTR1 VRNG RT SGND RUN1 ITH2 + COUT4 100µF ×2 20k //10k SGND PGOOD2 100k 0.01µF TRACK/SS1 TRACK/SS2 47pF 23.2k 20k PGOOD1 VOUT2 0.
LTC3838-1 TYPICAL APPLICATIONS VIN 4.5V TO 14V + CIN2 22µF ×4 CIN1 180µF 2.2Ω 1µF VIN 0.1µF 4.02k L1 0.4µH MT1 + COUT2 330µF ×2 SENSE2– SENSE1+ SENSE2+ BOOST1 BOOST2 0.1µF TG1 4.02k MT2 TG2 4.7µF MB1 SW2 DRVCC1 INTVCC DRVCC2 EXTVCC BG1 PGOOD1 VDFB2– PGOOD2 137k DTR2 VRNG RT SGND RUN1 PHASMD MODE/PLLIN CLKOUT RUN2 100k PGOOD 0.
LTC3838-1 TYPICAL APPLICATIONS + CIN2 10µF ×3 CIN1 220µF 2.2Ω 1µF VIN 20Ω VOUT1 5V 12A MT1 + COUT2 150µF ×2 SENSE1+ SENSE2+ BOOST1 BOOST2 TG1 0.1µF MT2 TG2 SW1 4.7µF 1µF MB1 20Ω SW2 DRVCC1 INTVCC DRVCC2 EXTVCC BG1 VOUT1 PGOOD1 0.01µF 220pF 53.6k PGOOD1 VDFB2– PGOOD2 TRACK/SS1 TRACK/SS2 22pF 137k 10k//45.3k 10k VOUTSENSE1– ITH1 DTR1 VRNG RT SGND RUN1 ITH2 COUT4 100µF 45.3k VDFB2+ 10k + VOUT2 3.3V 12A MB2 BG2 VOUTSENSE1+ RS2 0.
LTC3838-1 TYPICAL APPLICATIONS VIN 4.5V TO 14V + CIN1 180µF CIN2 22µF ×4 2.2Ω 1µF VIN 10Ω MT1 SENSE1+ SENSE2+ BOOST1 BOOST2 10Ω TG1 MT2 TG2 MB1 L2 0.3µH DB2 SW1 1µF 10Ω 0.1µF DB1 2.2Ω COUT1 100µF ×3 SENSE2– 1nF 0.1µF L1 0.3µH SENSE1– 1nF 10Ω RS1 0.004Ω LTC3838-1 SW2 DRVCC1 INTVCC 4.7µF DRVCC2 EXTVCC BG1 MB2 BG2 PGND VOUTSENSE1+ PGOOD1 VDFB2– PGOOD2 TRACK/SS1 TRACK/SS2 18.7k ITH1 ITH2 DTR1 VRNG DTR2 RT SGND RUN1 VOUT 3.3V 25A COUT2 100µF ×3 45.
LTC3838-1 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. UHF Package 38-Lead Plastic QFN (5mm × 7mm) (Reference LTC DWG # 05-08-1701 Rev C) 0.70 ±0.05 5.50 ±0.05 5.15 ±0.05 4.10 ±0.05 3.00 REF 3.15 ±0.05 PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC 5.5 REF 6.10 ±0.05 7.50 ±0.05 RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 5.00 ±0.10 0.75 ±0.05 PIN 1 NOTCH R = 0.30 TYP OR 0.35 × 45° CHAMFER 3.
LTC3838-1 TYPICAL APPLICATION 7V to 14V Input, 5V/7A and 3.3V/7A Dual Output, 2MHz, RSENSE, Step-Down Converter with EXTVCC Tied to 5V Output VIN 7V TO 14V + CIN2 10µF ×3 CIN1 39µF 2.2Ω 1µF VIN 10Ω 1nF 0.1µF VOUT1 5V 7A RS1 0.008Ω SENSE1+ SENSE2+ BOOST1 BOOST2 TG1 MT1 1µF 10Ω 0.1µF MT2 TG2 DB1 DB2 SW1 2.2Ω COUT1 47µF ×2 10Ω SENSE2– 1nF 10Ω L1 0.8µH LTC3838-1 SENSE1– 4.7µF MB1 SW2 DRVCC1 INTVCC DRVCC2 EXTVCC BG1 VOUT1 MB2 BG2 PGND 73.2k 100k PGOOD1 0.01µF 24.
