Datasheet

LTC3835
22
3835fd
APPLICATIONS INFORMATION
most critical frequency range of the feedback loop. The
output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance.
A second, more severe transient is caused by switching
in loads with large (>1µF) supply bypass capacitors. The
discharged bypass capacitors are effectively put in parallel
with C
OUT
, causing a rapid drop in V
OUT
. No regulator can
alter its delivery of current quickly enough to prevent this
sudden step change in output voltage if the load switch
resistance is low and it is driven quickly. If the ratio of
C
LOAD
to C
OUT
is greater than 1:50, the switch rise time
should be controlled so that the load rise time is limited
to approximately 25 • C
LOAD
. Thus a 10µF capacitor would
require a 250µs rise time, limiting the charging current
to about 200mA.
Design Example
As a design example, assume V
IN
= 12V(nominal), V
IN
=
22V(max), V
OUT
= 1.8V, I
MAX
= 5A, and f = 250kHz.
The inductance value is chosen first based on a 30% ripple
current assumption. The highest value of ripple current
occurs at the maximum input voltage. Tie the PLLLPF
pin to GND, generating 250kHz operation. The minimum
inductance for 30% ripple current is:
∆I
L
=
V
OUT
(f)(L)
1–
V
OUT
V
IN






A 4.7µH inductor will produce 23% ripple current and a
3.3µH will result in 33%. The peak inductor current will be
the maximum DC value plus one half the ripple current, or
5.84A, for the 3.3µH value. Increasing the ripple current will
also help ensure that the minimum on-time of 180ns is not
violated. The minimum on-time occurs at maxi-mum V
IN
:
t
ON(MIN)
=
V
OUT
V
IN(MAX)
f
=
1.8V
22V(250kHz)
= 327ns
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R
SENSE
≤
80mV
5.84A
≈ 0.012Ω
Choosing 1% resistors: R1 = 25.5k and R2 = 32.4k yields
an output voltage of 1.816V.
The power dissipation on the top side MOSFET can be easily
estimated. Choosing a Fairchild FDS6982S dual MOSFET
results in: R
DS(ON)
= 0.035Ω/0.022Ω, C
MILLER
= 215pF. At
maximum input voltage with T(estimated) = 50°C:
P
MAIN
=
1.8V
22V
5
( )
2
1+ (0.005)(50°C – 25°C)
[ ]
•
0.035Ω
( )
+ 22V
( )
2
5A
2






4Ω
( )
215pF
( )
•
1
5 – 2.3
+
1
2.3






300kHz
( )
= 332mW
A short-circuit to ground will result in a folded back
current of:
I
SC
=
25mV
0.01Ω
–
1
2
120ns(22V)
3.3µH






= 2.1A
with a typical value of R
DS(ON)
and d = (0.005/°C)(20) = 0.1.
The resulting power dissipated in the bottom MOSFET is:
P
SYNC
=
22V – 1.8V
22V
2.1A
( )
2
1.125
( )
0.022Ω
( )
=
100mW
which is less than under full-load conditions.
C
IN
is chosen for an RMS current rating of at least 3A at
temperature assuming only this channel is on. COUT is
chosen with an ESR of 0.02Ω for low output ripple. The
output ripple in continuous mode will be highest at the
maximum input voltage. The output voltage ripple due to
ESR is approximately:
V
ORIPPLE
= R
ESR
(∆I
L
) = 0.02Ω(1.67A) = 33mV
P–P