Datasheet
LTC3835-1
17
38351fc
APPLICATIONS INFORMATION
Phase-Locked Loop and Frequency Synchronization
The LTC3835-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOSFET
to be locked to the rising edge of an external clock signal
applied to the PLLIN/MODE pin. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external fi lter net-
work connected to the PLLLPF pin. The relationship between
the voltage on the PLLLPF pin and operating frequency, when
there is a clock signal applied to PLLIN/MODE, is shown in
Figure 6 and specifi ed in the Electrical Characteristics table.
Note that the LTC3835-1 can only be synchronized to an exter-
nal clock whose frequency is within range of the LTC3835-1’s
internal VCO, which is nominally 115kHz to 800kHz. This is
guaranteed to be between 140kHz and 650kHz. A simplifi ed
block diagram is shown in Figure 7.
PLLLPF PIN VOLTAGE (V)
0
FREQUENCY (kHz)
0.5 1 1.5 2
38351 F06
2.5
0
100
300
400
500
900
800
700
200
600
Figure 6. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3835-1 F07
PLLLPF
EXTERNAL
OSCILLATOR
PLLIN/
MODE
Figure 7. Phase-Locked Loop Block Diagram