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LTC3835-1

38351fc

TYPICAL APPLICATION

FEATURES

APPLICATIONS

DESCRIPTION

Low I

Synchronous

Step-Down Controller

L, LT, LTC, LTM, Burst Mode, and OPTI-LOOP are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5408150, 5481178, 5705919, 5929620, 6304066,

6498466, 6580258, 6611131.

High Efﬁ ciency Step-Down Converter

Efﬁ ciency and Power Loss

vs Load Current

Wide Output Voltage Range: 0.8V ≤ V

OUT

≤ 10V

Low Operating I

: 80μA

OPTI-LOOP

Compensation Minimizes C

OUT

±1% Output Voltage Accuracy

Wide V

Range: 4V to 36V Operation

Phase-Lockable Fixed Frequency 140kHz to 650kHz

Dual N-Channel MOSFET Synchronous Drive

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Output Current Foldback Limiting

Output Overvoltage Protection

Low Shutdown I

: 10μA

Selectable Continuous, Pulse-Skipping or

Burst Mode

Operation at Light Loads

Small 16-Lead Narrow SSOP or 3mm × 5mm

DFN Package

Automotive Systems

Telecom Systems

Battery-Operated Digital Devices

Distributed DC Power Systems

The LTC

3835-1 is a high performance step-down switch-

ing regulator controller that drives an all N-channel synchro-

nous power MOSFET stage. A constant-frequency current

mode architecture allows a phase-lockable frequency of

up to 650kHz.

The 80μA no-load quiescent current extends operating

life in battery powered systems. OPTI-LOOP compensa-

tion allows the transient response to be optimized over

a wide range of output capacitance and ESR values. The

LTC3835-1 features a precision 0.8V reference and a power

good output indicator. The 4V to 36V input supply range

encompasses a wide range of battery chemistries.

The TRACK/SS pin ramps the output voltage during start-

up. Current foldback limits MOSFET heat dissipation during

short-circuit conditions.

Comparison of LTC3835 and LTC3835-1

PART #

CLKOUT/

PHASMD EXTV

PGOOD PACKAGES

LTC3835 YES YES YES

FE20/4 × 5 QFN

LTC3835-1 NO NO NO

GN16/3 × 5 DFN

OUT

3.3V

150μF

0.01μF

4V TO 36V

SGND

PLLIN/MODE

SENSE

–

PLLLPF

RUN

TRACK/SS

INTV

PGND

LTC3835-1

3.3μH

0.012Ω

20k

38351 TA01

100pF

330pF

33k

62.5k

4.7μF

0.22μF

BOOST

10μF

LOAD CURRENT (mA)

EFFICIENCY (%)

POWER LOSS (mW)

0.01 0.1 1 10 100 1000 10000

38351 TA01b

0.001

1000

100

0.1

100000

10000

100

POWER LOSS

EFFICIENCY

= 12V; V

OUT

= 3.3V

Summary of content (28 pages)

PAGE 1
LTC3835-1 Low IQ Synchronous Step-Down Controller FEATURES DESCRIPTION n The LTC®3835-1 is a high performance step-down switching regulator controller that drives an all N-channel synchronous power MOSFET stage. A constant-frequency current mode architecture allows a phase-lockable frequency of up to 650kHz. n n n n n n n n n n n n n Wide Output Voltage Range: 0.
PAGE 2
LTC3835-1 ABSOLUTE MAXIMUM RATINGS (Note 1) Input Supply Voltage (VIN) ......................... 36V to –0.3V Top Side Driver Voltage (BOOST) ............... 42V to –0.3V Switch Voltage (SW) ..................................... 36V to –5V INTVCC, (BOOST-SW) ............................... 8.5V to –0.3V RUN, TRACK/SS ......................................... 7V to –0.3V SENSE+, SENSE– Voltages ........................ 11V to –0.3V PLLIN/MODE, PLLLPF .........................INTVCC to –0.
PAGE 3
LTC3835-1 ELECTRICAL CHARACTERISTICS The l denotes the speciﬁcations which apply over the full operating temperature range, otherwise speciﬁcations are at TA = 25°C. VIN = 12V, VRUN = 5V unless otherwise noted. SYMBOL PARAMETER Main Control Loop Regulated Feedback Voltage VFB Feedback Current IVFB Reference Voltage Line Regulation VREFLNREG Output Voltage Load Regulation VLOADREG CONDITIONS (Note 4); ITH Voltage = 1.2V (Note 4) VIN = 4V to 30V (Note 4) (Note 4) Measured in Servo Loop; ΔITH Voltage = 1.
PAGE 4
LTC3835-1 ELECTRICAL CHARACTERISTICS Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formulas: Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. See Applications Information. LTC3835GN-1: TJ = TA + (PD • 90°C/W) LTC3835EDHC-1: TJ = TA + (PD • 43.5°C/W) Note 6: Rise and fall times are measured using 10% and 90% levels. Delay times are measured using 50% levels.
PAGE 5
LTC3835-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Soft Start-Up Inductor Current at Light Load Tracking Start-Up VOUT2 2V/DIV FORCED CONTINUOUS MODE (MASTER) VOUT1 2V/DIV 2A/DIV Burst Mode OPERATION (SLAVE) VOUT 1V/DIV PULSESKIPPING MODE Total Input Supply Current vs Input Voltage EXTVCC Switchover and INTVCC Voltages vs Temperature SUPPLY CURRENT (μA) 300 250 300μA LOAD 200 150 NO LOAD 50 0 5 10 25 20 15 INPUT VOLTAGE (V) 35 30 5.50 5.8 5.45 5.40 5.6 5.
PAGE 6
LTC3835-1 TYPICAL PERFORMANCE CHARACTERISTICS Quiescent Current vs Temperature Foldback Current Limit 80 60 40 20 10 90 INPUT CURRENT (μA) 100 85 80 75 75 90 1.00 1.15 0.95 RUN PIN VOLTAGE (V) 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 0.85 0.55 75 0.50 –45 –30 –15 90 0 15 30 45 60 TEMPERATURE (°C) 75 38351 G19 798 796 794 0 15 30 45 60 TEMPERATURE (°C) 75 90 38351 G21 Oscillator Frequency vs Temperature 800 700 VOUT = 3.
PAGE 7
LTC3835-1 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. Oscillator Frequency vs Input Voltage Undervoltage Lockout Threshold vs Temperature 4.2 Shutdown Current vs Temperature 404 12 402 10 3.9 3.8 FREQUENCY (kHz) INTVCC VOLTAGE (V) 4.0 RISING 3.7 3.6 3.5 SHUTDOWN CURRENT (μA) 4.1 400 398 396 FALLING 3.4 394 8 6 4 2 3.3 3.
PAGE 8
LTC3835-1 PIN FUNCTIONS (DHC Package/GN Package) RUN (Pin 13/Pin 13): Digital Run Control Input for Controller. Forcing this pin below 0.7V shuts down all controller functions, reducing the quiescent current that the LTC3835-1 draws to approximately 10μA. Input. When an external clock is applied to this pin, the phase-locked loop will force the rising TG signal to be synchronized with the rising edge of the external clock. In this case, an R-C ﬁlter must be connected to the PLLLPF pin.
PAGE 9
LTC3835-1 OPERATION (Refer to Functional Diagram) Main Control Loop Shutdown and Start-Up (RUN and TRACK/SS Pins) The LTC3835-1 uses a constant-frequency, current mode step-down architecture. During normal operation, each external top MOSFET is turned on when the clock sets the RS latch, and is turned off when the main current comparator, ICMP, resets the RS latch.
PAGE 10
LTC3835-1 OPERATION (Refer to Functional Diagram) Light Load Current Operation (Burst Mode Operation, Pulse-Skipping, or Continuous Conduction) (PLLIN/MODE Pin) The LTC3835-1 can be enabled to enter high efﬁciency Burst Mode operation, constant-frequency pulse-skipping mode, or forced continuous conduction mode at low load currents. To select Burst Mode operation, tie the PLLIN/ MODE pin to a DC voltage below 0.8V (e.g., SGND). To select forced continuous operation, tie the PLLIN/MODE pin to INTVCC.
PAGE 11
LTC3835-1 OPERATION (Refer to Functional Diagram) The typical capture range of the LTC3835-1’s phaselocked loop is from approximately 115kHz to 800kHz, with a guarantee to be between 140kHz and 650kHz. In other words, the LTC3835-1’s PLL is guaranteed to lock to an external clock source whose frequency is between 140kHz and 650kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling).
PAGE 12
LTC3835-1 APPLICATIONS INFORMATION Accepting larger values of ΔIL allows the use of low inductances, but results in higher output voltage ripple and greater core losses. A reasonable starting point for setting ripple current is ΔIL = 0.3(IMAX). The maximum ΔIL occurs at the maximum input voltage. The inductor value also has secondary effects. The transition to Burst Mode operation begins when the average inductor current required results in a peak current below 10% of the current limit determined by RSENSE.
PAGE 13
LTC3835-1 APPLICATIONS INFORMATION The MOSFET power dissipations at maximum output current are given by: PMAIN = ( VOUT I VIN MAX )2 (1+ δ )RDS(ON) + ⎛ ⎞ ( VIN)2 ⎜⎝ IMAX (R )(C )• 2 ⎟⎠ DR MILLER ⎡ 1 1 ⎤ + ⎢ ⎥ f – V V V THMIN ⎦ ⎣ INTVCC THMIN () PSYNC = ( VIN – VOUT IMAX VIN )2 (I + δ )RDS(ON) where δ is the temperature dependency of RDS(ON) and RDR (approximately 2Ω) is the effective driver resistance at the MOSFET ’s Miller threshold voltage.
PAGE 14
LTC3835-1 APPLICATIONS INFORMATION Setting Output Voltage 200 VOUT ⎛ R ⎞ = 0.8 V • ⎜ 1+ B ⎟ ⎝ R ⎠ 100 0 INPUT CURRENT (μA) The LTC3835-1 output voltage is set by an external feedback resistor divider carefully placed across the output, as shown in Figure 1. The regulated output voltage is determined by: –100 –200 –300 –400 –500 A –600 To improve the frequency response, a feed-forward capacitor, CFF , may be used.
PAGE 15
LTC3835-1 APPLICATIONS INFORMATION Alternatively, the TRACK/SS pin can be used to track two (or more) supplies during start-up, as shown qualitatively in Figures 4a and 4b. To do this, a resistor divider should be connected from the master supply (VX) to the TRACK/ SS pin of the slave supply (VOUT), as shown in Figure 5.
PAGE 16
LTC3835-1 APPLICATIONS INFORMATION High input voltage applications in which large MOSFETs are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3835-1 to be exceeded. The INTVCC current, which is dominated by the gate charge current, is supplied by the 5.25V VIN LDO. Power dissipation for the IC in this case is equal to VIN • IINTVCC. The gate charge current is dependent on operating frequency as discussed in the Efﬁciency Considerations section.
PAGE 17
LTC3835-1 APPLICATIONS INFORMATION Phase-Locked Loop and Frequency Synchronization The LTC3835-1 has a phase-locked loop (PLL) comprised of an internal voltage-controlled oscillator (VCO) and a phase detector. This allows the turn-on of the top MOSFET to be locked to the rising edge of an external clock signal applied to the PLLIN/MODE pin. The phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators.
PAGE 18
LTC3835-1 APPLICATIONS INFORMATION If the external clock frequency is greater than the internal oscillator’s frequency, fOSC, then current is sourced continuously from the phase detector output, pulling up the PLLLPF pin. When the external clock frequency is less than fOSC, current is sunk continuously, pulling down the PLLLPF pin. If the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference.
PAGE 19
LTC3835-1 APPLICATIONS INFORMATION Efﬁciency Considerations The percent efﬁciency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efﬁciency and which change would produce the most improvement. Percent efﬁciency can be expressed as: %Efﬁciency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power.
PAGE 20
LTC3835-1 APPLICATIONS INFORMATION Checking Transient Response The regulator loop response can be checked by looking at the load current transient response. Switching regulators take several cycles to respond to a step in DC (resistive) load current. When a load step occurs, VOUT shifts by an amount equal to ΔILOAD (ESR), where ESR is the effective series resistance of COUT.
PAGE 21
LTC3835-1 APPLICATIONS INFORMATION Design Example As a design example, assume VIN = 12V(nominal), VIN = 22V(max), VOUT = 1.8V, IMAX = 5A and f = 250kHz. The inductance value is chosen ﬁrst based on a 30% ripple current assumption. The highest value of ripple current occurs at the maximum input voltage. Tie the PLLLPF pin to GND, generating 250kHz operation. The minimum inductance for 30% ripple current is: ΔIL = VOUT f L ( )( ) ⎛ VOUT ⎞ ⎜⎝ 1– V ⎟⎠ IN tON(MIN) = VOUT VIN(MAX )f = 1.
PAGE 22
LTC3835-1 APPLICATIONS INFORMATION PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the IC. These items are also illustrated graphically in the layout diagram of Figure 8. The Figure 9 illustrates the current waveforms present in the various branches of the synchronous regulator operating in the continuous mode. Check the following in your layout: 1. Is the top N-channel MOSFET M1 located within 1cm of CIN? 2.
PAGE 23
LTC3835-1 APPLICATIONS INFORMATION SW VIN L1 RSENSE VOUT RIN CIN D1 COUT RL1 3835-1 F09 BOLD LINES INDICATE HIGH SWITCHING CURRENT. KEEP LINES TO A MINIMUM LENGTH. Figure 9. Branch Current Waveforms PC Board Layout Debugging It is helpful to use a DC-50MHz current probe to monitor the current in the inductor while testing the circuit. Monitor the output switching node (SW pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well.
PAGE 24
LTC3835-1 TYPICAL APPLICATIONS High Efﬁciency 9.5V, 3A Step-Down Converter PLLLPF TG RUN 0.01μF VIN TRACK/SS CB 0.22μF BOOST ITH 560pF 35k LTC3835-1 CIN 10μF M1 7.2μH 0.012Ω SW VIN 4V TO 36V VOUT 9.5V 3A 100pF SGND 39.2k COUT 150μF INTVCC 4.7μF PLLIN/MODE VFB M2 BG SENSE– 432k SENSE+ PGND 38351 TA02 High Efﬁciency 12V to 1.8V, 2A Step-Down Converter PLLLPF TG RUN 0.01μF VIN TRACK/SS CB 0.22μF BOOST ITH 330pF 33k LTC3835-1 0.020Ω VIN 12V VOUT 1.
PAGE 25
LTC3835-1 TYPICAL APPLICATIONS High Efﬁciency 5V, 5A Step-Down Converter 0.01μF PLLLPF VIN RUN TG TRACK/SS CB 0.22μF M1 BOOST ITH 470pF LTC3835-1 3.3μH CIN 10μF 0.012Ω SW VIN 4V TO 36V VOUT 5V 5A 100pF 10k SGND 69.8k COUT 150μF INTVCC 4.7μF PLLIN/MODE VFB M2 BG SENSE– 365k SENSE+ PGND 38351 TA04 High Efﬁciency 1.2V, 5A Step-Down Converter GND 0.01μF PLLLPF VIN RUN TG TRACK/SS CB 0.22μF BOOST ITH 2.2nF 10k LTC3835-1 0.012Ω SW VOUT 1.2V 5A COUT 150μF INTVCC 4.
PAGE 26
LTC3835-1 PACKAGE DESCRIPTION DHC Package 16-Lead Plastic DFN (5mm × 3mm) (Reference LTC DWG # 05-08-1706) 0.65 ±0.05 3.50 ±0.05 1.65 ±0.05 2.20 ±0.05 (2 SIDES) PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 4.40 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 5.00 ±0.10 (2 SIDES) R = 0.20 TYP 3.00 ±0.10 (2 SIDES) 9 0.40 ± 0.10 16 1.65 ± 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) PIN 1 NOTCH (DHC16) DFN 1103 8 0.200 REF 1 0.25 ± 0.05 0.50 BSC 0.75 ±0.05 4.40 ±0.10 (2 SIDES) 0.
PAGE 27
LTC3835-1 PACKAGE DESCRIPTION GN Package 16-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .189 – .196* (4.801 – 4.978) .045 ±.005 16 15 14 13 12 11 10 9 .254 MIN .009 (0.229) REF .150 – .165 .229 – .244 (5.817 – 6.198) .0165 ±.0015 .150 – .157** (3.810 – 3.988) .0250 BSC RECOMMENDED SOLDER PAD LAYOUT 1 .015 ± .004 s 45° (0.38 ± 0.10) .007 – .0098 (0.178 – 0.249) 2 3 4 5 6 7 .0532 – .0688 (1.35 – 1.75) 8 .004 – .0098 (0.102 – 0.249) 0° – 8° TYP .016 – .050 (0.406 – 1.
PAGE 28
LTC3835-1 TYPICAL APPLICATION PLLLPF TG RUN 0.01μF VIN TRACK/SS CB 0.22μF L1 3.3μH BOOST ITH 1200pF LTC3835-1 DB CMDSH-3 SGND 68.1k 0.012Ω SW 100pF 10k CIN 10μF VOUT 3.3V 5A COUT 150μF INTVCC 4.7μF PLLIN/MODE VFB VIN 4V TO 36V BG SENSE– 215k SENSE+ PGND 39pF 38351 TA06 M1, M2: Si7848DD L1: CDEP 105-3R2M COUT: SANYO 10TPD150M Figure 10. High Efﬁciency 3.