Datasheet

8
LTC3834-1
38341f
FU CTIO AL DIAGRA
U
U
W
SWITCH
LOGIC
+
–
V
IN
V
IN
INTV
CC
-0.5V
0.8V
FC
BURSTEN
CLK
+
–
+
–
–
+
INTERNAL
SUPPLY
R
LP
C
LP
PLLIN/MODE
INTV
CC
SGND
+
LDO
5.25V
SW
SHDN
SLEEP
0.4V
TOP
BOOST
TG
C
B
C
IN
D
D
B
PGND
BOT
BG
INTV
CC
INTV
CC
V
IN
C
OUT
V
OUT
3834-1 FD
R
SENSE
R
B
V
FB
DROP
OUT
DET
BOT
TOP ON
S
R
Q
Q
OSCILLATOR
PHASE DET
PLLLPF
PLLIN/MODE
FC
BURSTEN
EA
0.88V
0.80V
TRACK/SS
OV
V
FB
0.5μA
1μA
6V
R
A
–
+
R
C
TRACK/SS
I
TH
C
C
C
C2
C
SS
2(V
FB
)
0.45V
SLOPE
COMP
6mV
+
–
–
+
SENSE
–
SENSE
+
ICMP IR
B
RUN
+– –+
F
IN
L
SHDN
ler functions, reducing the quiescent current that the
LTC3834-1 draws to approximately 4μA.
SENSE
–
(Pin 14/Pin 14): The (–) Input to the Differential
Current Comparator.
SENSE
+
(Pin 15/Pin 15): The (+) Input to the Differential
Current Comparator. The I
TH
pin voltage and controlled
offsets between the SENSE
–
and SENSE
+
pins in conjunc-
tion with R
SENSE
set the current trip threshold.
PLLIN/MODE (Pin 16/Pin 16): External Synchronization
Input to Phase Detector and Forced Continuous Control
Input. When an external clock is applied to this pin, the
phase-locked loop will force the rising TG signal to be
synchronized with the rising edge of the external clock. In
this case, an R-C filter must be connected to the PLLLPF
pin. When not synchronizing to an external clock, this
input determines how the LTC3834-1 operates at light
loads. Pulling this pin below 0.7V selects Burst Mode
operation. Tying this pin to INTV
CC
forces continuous
inductor current operation. Tying this pin to a voltage
greater than 0.9V and less than INTV
CC
selects pulse-
skipping operation.
Exposed Pad (Pin 17, DHC Package): SGND. Must be
soldered to PCB.
UU
U
PI FU CTIO S
(DHC Package/GN Package)