Datasheet

22
LTC3834-1
38341f
APPLICATIO S I FOR ATIO
WUUU
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
IC. These items are also illustrated graphically in the
layout diagram of Figure 8. The Figure 9 illustrates the
current waveforms present in the various branches of the
synchronous regulator operating in the continuous mode.
Check the following in your layout:
1. Is the top N-channel MOSFET M1 located within 1cm
of C
IN
?
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return
of C
INTVCC
must return to the combined C
OUT
(–) termi-
nals. The path formed by the top N-channel MOSFET,
Schottky diode and the C
IN
capacitor should have short
leads and PC trace lengths. The output capacitor (–)
terminals should be connected as close as possible to
the (–) terminals of the input capacitor by placing the
capacitors next to each other and away from the Schottky
loop described above.
3. Does the LTC3834-1 V
FB
pin resistive divider connect to
the (+) terminals of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground. The feedback resistor connections should not
be along the high current input feeds from the input
capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together
with minimum PC trace spacing? The filter capacitor
between SENSE
+
and SENSE
–
should be as close as
possible to the IC. Ensure accurate current sensing with
Kelvin connections at the SENSE resistor.
5. Is the INTV
CC
decoupling capacitor connected close to
the IC, between
the INTV
CC
and the power ground pins?
This capacitor carries the MOSFET drivers current
peaks. An additional 1μF ceramic capacitor placed
immediately next to the INTV
CC
and PGND pins can help
improve noise performance substantially.
6. Keep the switching node (SW), top gate node (TG), and
boost node (BOOST) away from sensitive small-signal
nodes, especially from the opposites channel’s voltage
and current sensing feedback pins. All of these nodes
have very large and fast moving signals and therefore
should be kept on the “output side” of the LTC3834-1
and occupy minimum PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on the
same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feed-
back resistive divider and the SGND pin of the IC.
Figure 8. LTC3834-1 Recommended Printed Circuit Layout Diagram
C
B
D
B
C
INTVCC
+
C
IN
D1
Optional
1μF
CERAMIC
M1 M2
+
C
VIN
V
IN
R
IN
TRACK/SS
SENSE
+
SENSE
–
V
FB
PLLLPF
PLLIN/MODE
RUN
I
TH
SGND
TG
SW
BOOST
V
IN
BG
INTV
CC
PGND
LTC3834EGN-1
L1
C
OUT
V
OUT
GND
+
R
SENSE
f
IN
3834-1 F08