Datasheet

17
LTC3834-1
38341f
APPLICATIO S I FOR ATIO
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Phase-Locked Loop and Frequency Synchronization
The LTC3834-1 has a phase-locked loop (PLL) comprised
of an internal voltage-controlled oscillator (VCO) and a
phase detector. This allows the turn-on of the top MOS-
FET to be locked to the rising edge of an external clock
signal applied to the PLLIN/MODE pin. The phase detector
is an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
filter network connected to the PLLLPF pin. The relation-
ship between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to PLLIN/
MODE, is shown in Figure 6 and specified in the Electrical
Characteristics table. Note that the LTC3834-1 can only be
synchronized to an external clock whose frequency is
within range of the LTC3834-1’s internal VCO, which is
nominally 115kHz to 800kHz. This is guaranteed to be
between 140kHz and 650kHz. A simplified block diagram
is shown in Figure 7.
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3834-1 F07
PLLLPF
EXTERNAL
OSCILLATOR
PLLIN/
MODE
Figure 6. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
Figure 7. Phase-Locked Loop Block Diagram
PLLLPF VOLTAGE (V)
400
500
700
800
900
1.5
3834 G28
300
200
0 0.5
1.0 2.0 2.5
100
0
600
FREQUENCY (kHz)