Datasheet

LTC3833
28
3833f
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3833.
• Multilayer boards with dedicated ground layers are
preferable for reduced noise and for heat sinking
purposes. Use wide rails and/or entire planes for V
IN
,
V
OUT
and PGND nodes for good filtering and minimal
copper loss. If a ground layer is used, then it should
be immediately below (and/or above) the routing layer
for the power train components which consist of C
IN
,
power MOSFETs, inductor, sense resistor (if used) and
C
OUT
. Flood unused areas of all layers with copper for
better heat sinking.
• Keep signal and power grounds separate except at the
point where they are shorted together. Short signal and
power ground together only at a single point with a nar-
row PCB trace (or single via in a multilayer board). All
power train components should be referenced to power
ground and all small-signal components (e.g., C
ITH1
,
R
T
, C
SS
etc.) should be referenced to signal ground.
• Place C
IN
, power MOSFETs, inductor, sense resistor (if
used), and primary C
OUT
capacitors close together in
one compact area. The SW node should be compact
but be large enough to handle the inductor currents
without large copper losses. Connect the drain of the
topside MOSFET as close as possible to the (+) plate of
C
IN
capacitor(s) that provides the bulk of the AC current
(these are normally the ceramic capacitors), and con-
nect the source of the bottom side MOSFET as close as
possible to the (–) terminal of the same C
IN
capacitor(s).
The high dI/dt loop formed by C
IN
, the top MOSFET,
and the bottom MOSFET should have short leads and
PCB trace lengths to minimize high frequency EMI and
voltage stress from inductive ringing. The (–) terminal
of the primary C
OUT
capacitor(s) which filter the bulk
of the inductor ripple current (these are normally the
ceramic capacitors) should also be connected close to
the (–) terminal of C
IN
.
• Place BOOST, TG, SW, BG and PGND pins facing the
power train components. Keep high dV/dt signals on
BOOST, TG, SW and BG away from sensitive small-signal
traces and components.
• For R
SENSE
current sensing, place the sense resistor
close to the inductor on the output side. Use a Kelvin
(4-wire) connection across the sense resistor and
route the traces together as a differential pair. RC filter
the differential sense signal close to SENSE
+
/SENSE
–
pins, placing the filter capacitor as close as possible
to the pins. For DCR sensing, Kelvin connect across
the inductor and place the DCR sensing resistor closer
to the SW node and further away from the SENSE
+
/
SENSE
–
pins. Place the DCR capacitor close to the
SENSE
+
/SENSE
–
pins.
• Place the resistive feedback divider R
FB1/2
as close as
possible to V
OSNS
+
/V
OSNS
–
pins and route the remote
output and ground traces together as a differential
pair and terminate as close to the regulation point as
possible (preferably Kelvin connect across the capacitor
at the remote output point).
• Place the ceramic C
VCC
capacitor as close as possible
to INTV
CC
and PGND pins. Likewise, the C
B
capacitor
should be as close as possible to BOOST and SW pins.
These capacitors provide the gate charging currents for
the power MOSFETs.
• Place small-signal components as close to their respec-
tive pins as possible. This minimizes the possibility of
PCB noise coupling into these pins. Give priority to
V
OSNS
+
/V
OSNS
–
, SENSE
+
/SENSE
–
, ITH, RT and V
RNG
pins. Use sufficient isolation when routing a clock signal
into MODE/PLLIN pin so that the clock does not couple
into sensitive small-signal pins.
• Filter the V
IN
input to the LTC3833 with a simple RC
filter close to the pin. The RC filter should be referenced
to signal ground.
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