Datasheet

LTC3833
23
3833f
APPLICATIONS INFORMATION
where t
ON(MIN)
is the effective minimum on-time for the
switching regulator. As the equation shows, reducing the
operating frequency will alleviate the minimum duty cycle
constraint.
If the application requires a smaller than minimum duty
cycle, the output voltage will still remain in regulation, but
the switching frequency will decrease from its programmed
value or lose frequency synchronization if using an external
clock. Depending on the application, this may not be of
critical importance.
For applications that require relatively low on-times,
proper caution has to be taken when choosing the top
power MOSFET. If a high Q
g
MOSFET is chosen such that
the on-time is not sufficient to fully turn the MOSFET on,
there will be significant losses in efficiency as a result
of larger R
DS(ON)
resistance and possibly failure of the
MOSFET due to significant heat dissipation.
The minimum off-time is the smallest duration of time
that the top power MOSFET ’s gate can be turned off and
then immediately turned back on. This minimum off-time
includes the time to turn on the bottom power MOSFET ’s
gate and turn it back off along with the dead time delays
from top MOSFET off to bottom MOSFET on and bottom
MOSFET off to top MOSFET on. The minimum off-time
that the LTC3833 can achieve is 90ns.
The effective minimum off-time of the switching regulator
is defined as the shortest period of time that the SW node
can stay low. This effective minimum off-time can vary
from the LTC3833’s 90ns of minimum off-time. The main
factor impacting the effective minimum off-time is the top
and bottom power MOSFETs’ gate charging characteristics,
including Q
g
and turn-on/off delays. These characteristics
can either extend or shorten the SW node’s minimum
off-time as compared to the LTC3833’s minimum off-time.
Large size (high Q
g
) power MOSFETs generally tend to
increase the effective minimum off-time due to longer
gate charging and discharging times. On the other hand,
imbalances in turn-on and turn-off delays could reduce
the effective minimum off-time.
The minimum off-time limit imposes a maximum duty
cycle of:
D
MAX
= 1 – f • t
OFF(MIN)
where t
OFF(MIN)
is the effective minimum off-time of the
switching regulator. Reducing the operating frequency al-
leviates the maximum duty cycle constraint. If the maximum
duty cycle is reached, due to a drooping input voltage for
example, then the output will drop out of regulation. The
minimum input voltage to avoid dropout is:
V
IN(MIN)
=
V
OUT
D
MAX
At the onset of dropout, there is a region of V
IN
about
500mV that generates two discrete off-times, one being
the minimum off-time and the other being an off-time that
is about 40ns to 60ns larger than the minimum off-time.
This secondary off-time is due to the longer delay in trip-
ping the internal current comparator. The two off-times
average out to the required duty cycle to keep the output
in regulation with the output ripple remaining the same.
However, there is higher SW node jitter, especially appar-
ent when synchronized to an external clock. Depending
on the application, this may not be of critical importance.
DEAD-TIME
DELAYS
NEGATIVE
INDUCTOR
CURRENT
IN FCM
DURING BG-TG DEAD TIME,
NEGATIVE INDUCTOR CURRENT
WILL FLOW THROUGH TOP MOSFET’S
BODY DIODE TO PRECHARGE SW NODE
3833 F08
TG-SW
(V
GS
OF
TOP MOSFET)
BG
(V
GS
OF
BOTTOM MOSFET)
I
L
SW
0
V
IN
+
–
I
L
V
IN
L
SW
DURING TG-BG DEAD TIME,
THE RATE OF SW NODE DISCHARGE
WILL DEPEND ON THE CAPACITANCE
ON THE SW NODE AND INDUCTOR
CURRENT MAGNITUDE
L
TOTAL CAPACITANCE
ON THE SW NODE
I
L
Figure 8. Light Loading On-Time Extension with Forced
Continuous Mode Operation