Datasheet

LTC3833
21
3833f
APPLICATIONS INFORMATION
the internally calculated on-time differs significantly from
the real on-time required by the application. For example,
if there are differences between the local output point and
the remotely regulated output point due to line losses, then
the internally calculated on-time will be inaccurate. Lower
efficiencies in the switching regulator can also cause the
real on-time to be significantly different from the internally
calculated on-time (see Efficiency Considerations). For
these circumstances, the voltage on the V
OUT
pin can
be programmed with a resistive divider from INTV
CC
or
from the regulator’s output itself. Note that there is a 500k
nominal resistance looking into the V
OUT
pin.
The PLL adjusted on-time achieved after phase locking is
the steady-state on-time required by the switching regula-
tor, and if the V
OUT
programmed on-time is substantially
equal to this steady-state on-time, then the PLL system
does not have to use its ±30% frequency lock range for
systematic corrections. Instead the lock range can be used
to correct for component variations or other operating point
conditions. If needed, the V
OUT
pin can be programmed
to achieve the steady-state on-time as required by the
application and therefore maintain constant frequency
operation.
If the application requires very low on-times approaching
minimum on-time, the PLL system may not be able to
maintain a ±30% synchronization range. In fact, there is
a possibility of losing phase/frequency lock at minimum
on-time, and definitely losing phase/frequency lock for
applications requiring less than minimum on-time. This
is discussed further under Minimum On-Time, Minimum
Off-Time and Dropout Operation.
During dynamic transient conditions either in the line or
load (e.g., load step or release), the LTC3833 may lose
phase and frequency lock in the process of achieving faster
transient response. For large slew rates (e.g., 10A/µs),
phase and frequency lock will be lost (see Figure 7) until
the system returns back to a steady-state condition at
which point the device will resume frequency lock and
eventually achieve phase lock to the external clock. For
relatively small slew rates (10A/s), phase and frequency
lock can still be maintained.
Figure 6b. Setup for Coincident and Ratiometric Tracking
Figure 6a. Two Different Modes of Output Tracking
TIME
Coincident Tracking
EXTERNAL
SUPPLY
EXTERNAL
SUPPLY
V
OUT
VOLTAGE
V
OUT
TIME
3833 F06
Ratiometric Tracking
VOLTAGE
R
FB2
EXT. V
R
FB1
Coincident Tracking Setup
TO
TRACK/SS
R
FB2
V
OUT
TO V
OSNS
+
R
FB1
TO V
OSNS
–
R1
EXT. V
R2
R1+ R2
≥
R2
TO
TRACK/SS
R
FB2
V
OUT
TO V
OSNS
+
R
FB1
TO V
OSNS
–
3833 F06b
Ratiometric Tracking Setup
0.6V
EXT. V