Datasheet
LTC3833
17
3833f
APPLICATIONS INFORMATION
Ensure that R1 has a power rating higher than this value.
If high efficiency is necessary at light loads, consider this
power loss when deciding whether to use DCR sensing or
R
SENSE
sensing. Light load power loss can be modestly
higher with a DCR network than with a sense resistor due
to the extra switching losses incurred through R1. However,
DCR sensing eliminates a sense resistor, reduces conduc-
tion losses and provides higher efficiency at heavy loads.
Peak efficiency is about the same with either method.
To maintain a good signal-to-noise ratio for the current
sense signal, use a minimum ∆V
SENSE
of 10mV. For a
DCR sensing application, the actual ripple voltage will be
determined by:
∆V
SENSE
=
V
IN
– V
OUT
R1• C1
•
V
OUT
V
IN
• f
Power MOSFET Selection
Two external power MOSFETs must be selected for the
LTC3833 controller: one N-channel MOSFET for the top
(main) switch and one N-channel MOSFET for the bottom
(synchronous) switch. The peak-to-peak drive levels are
set by the INTV
CC
voltage. This voltage is typically 5.3V.
Consequently, logic-level threshold MOSFETs must be
used in most applications. Pay close attention to the
BV
DSS
specification for the MOSFETs as well; most of the
logic-level MOSFETs are limited to 30V or less. Selection
criteria for the power MOSFETs include the on-resistance,
R
DS(ON)
, Miller capacitance, C
MILLER
, input voltage and
maximum output current. Miller capacitance, C
MILLER
,
can be approximated from the gate charge curve usu-
ally provided on the MOSFET manufacturers’ data sheet.
C
MILLER
is equal to the increase in gate charge along the
horizontal axis where the curve is approximately flat, di-
vided by the specified change in V
DS
. This result is then
multiplied by the ratio of the application V
DS
to the gate
charge curve specified V
DS
. When the IC is operating in
continuous mode, the duty cycles for the top and bottom
MOSFETs are given by:
Main Switch Duty Cycle D
TOP
( )
=
V
OUT
V
IN
Synchronous Switch Duty Cycle D
BOT
( )
= 1–
V
OUT
V
IN
The MOSFET power dissipations at maximum output
current are given by:
P
TOP
= D
TOP
•I
OUT(MAX)
2
• R
DS(ON)(MAX)
1+ δ
( )
+ V
IN
2
•
I
OUT(MAX)
2
• C
MILLER
R
TG(HI)
V
INTVCC
– V
MILLER
+
R
TG(LO)
V
MILLER
• f
P
BOT
= D
BOT
• I
OUT(MAX)
2
• R
DS(ON)(MAX)
(1 + δ)
where D
TOP
and D
BOT
are the duty cycles of the top MOSFET
and bottom MOSFET respectively, δ is the temperature de-
pendency of R
DS(ON)
, R
TG(HI)
is the TG pull-up resistance,
and R
TG(LO)
is the TG pull-down resistance. V
MILLER
is the
Miller effect V
GS
voltage and is taken graphically from the
MOSFET’s data sheet.
Both MOSFETs have I
2
R losses while the topside N-channel
equation includes an additional term for transition losses,
which are highest at high input voltages. For V
IN
< 20V,
the high current efficiency generally improves with larger
MOSFETs, while for V
IN
> 20V, the transition losses rapidly
increase to the point that the use of a higher R
DS(ON)
device
with lower C
MILLER
actually provides higher efficiency. The
synchronous MOSFET losses are greatest at high input
voltage when the top switch duty factor is low or during
short-circuit when the synchronous switch is on close to
100% of the period.
The term (1 + δ) is generally given for a MOSFET in the
form of a normalized R
DS(ON)
vs temperature curve, but
δ = 0.005/°C • (T
J
– T
A
) can be used as an approximation
for low voltage MOSFETs (T
J
is estimated junction tem-
perature of the MOSFET and T
A
is ambient temperature).
C
IN
and C
OUT
Selection
In continuous mode, the source current of the top N-chan-
nel MOSFET is a square wave of duty cycle V
OUT
/V
IN
. To
prevent large voltage transients, a low ESR input capacitor
sized for the maximum RMS current must be used. The
maximum RMS capacitor current is given by:
I
RMS
≅I
OUT(MAX)
•
V
OUT
V
IN
•
V
IN
V
OUT
– 1
This formula has a maximum at V
IN
= 2V
OUT
, where I
RMS
= I
OUT(MAX)
/2. This simple worst-case condition is com-
monly used for design because even significant deviations