Datasheet

18
LTC3832/LTC3832-1
sn3832 3832fs
APPLICATIO S I FOR ATIO
WUUU
1. In general, layout should begin with the location of the
power devices. Be sure to orient the power circuitry so that
a clean power flow path is achieved. Conductor widths
should be maximized and lengths minimized. After you are
satisfied with the power path, the control circuitry should
be laid out. It is much easier to find routes for the relatively
small traces in the control circuits than it is to find
circuitous routes for high current paths.
2. The GND and PGND pins should be shorted directly at
the LTC3832. This helps to minimize internal ground dis-
turbances in the LTC3832 and prevent differences in ground
potential from disrupting internal circuit operation. This
connection should then tie into the ground plane at a single
point, preferably at a fairly quiet point in the circuit such as
close to the output capacitors. This is not always practical,
however, due to physical constraints. Another reasonably
good point to make this connection is between the output
capacitors and the source connection of the bottom
MOSFET Q2. Do not tie this single point ground in the trace
run between the Q2 source and the input capacitor ground,
as this area of the ground plane will be very noisy.
3. The small-signal resistors and capacitors for frequency
compensation and soft-start should be located very close
to their respective pins and the ground ends connected to
the signal ground pin through a separate trace. Do not
connect these parts to the ground plane!
4. The V
CC
, PV
CC1
and PV
CC2
decoupling capacitors should
be as close to the LTC3832 as possible. The 4.7µF and 1µF
bypass capacitors shown at V
CC
, PV
CC1
and PV
CC2
will help
provide optimum regulation performance.
5. The (+) plate of C
IN
should be connected as close as
possible to the drain of the upper MOSFET, Q1. An additional
1µF ceramic capacitor between V
IN
and power ground is
recommended.
6. The SENSE and V
FB
pins are very sensitive to pickup from
the switching node. Care should be taken to isolate SENSE
and V
FB
from possible capacitive coupling to the inductor
switching signal. Connecting the SENSE
+
and SENSE
–
close
to the load can significantly improve load regulation.
7. Kelvin sense I
MAX
and I
FB
at Q1’s drain and source pins.
PV
CC1
G1
I
MAX
I
FB
SENSE
+
G2
FB
SENSE
–
FREQSET
SHDN
COMP
SS
V
CC
LTC3832
PV
CC2
GND PGND
+
+
1µF
GND
GND
NC
100Ω
1k
V
IN
Q1A
Q2
PGND
Q1B
C
IN
+
C
OUT
3832 F11
V
OUT
L
O
C
SS
C1
C
C
4.7µF
NC
R
C
1µF
0.1µF
PGND
PV
CC
Figure 11. Typical Schematic Showing Layout Considerations