Datasheet

LTC3828
7
3828fc
Load Step: Burst Mode Operation
(Figure 14)
Load Step: Continuous Mode
(Figure 14)
PIN FUNCTIONS
(SSOP/QFN)
Input Source/Capacitor
Instantaneous Current
(Figure 14)
3828 G22
V
OUT1
100mV/DIV
V
OUT2
100mV/DIV
I
L1
2A/DIV
50µs/DIV
V
IN
= 12V
V
OUT1
= 5V
V
OUT2
= 3.3V
LOAD STEP = 0A TO 3A
WITH RATIOMETRIC TRACKING
3828 G23
V
OUT1
100mV/DIV
V
OUT2
100mV/DIV
I
L1
2A/DIV
50µs/DIV
V
IN
= 12V
V
OUT1
= 5V
V
OUT2
= 3.3V
LOAD STEP = 0A TO 3A
WITH RATIOMETRIC TRACKING
3828 G24
SW1
20V/DIV
SW2
20V/DIV
I
IN
25A/DIV
V
IN
RIPPLE
50mV/DIV
500ns/DIV
V
IN
= 12V
V
OUT1
= 5V
V
OUT2
= 3.3V
I
OUT5
= I
OUT3.3
= 2A
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C unless otherwise noted.
Burst Mode Operation
(Figure 14)
Constant Frequency (Burst
Inhibit) Operation (Figure 14)
3828 G25
V
OUT
20mV/DIV
I
L
1A/DIV
100µs/DIV
V
IN
= 12V
V
OUT
= 5V
V
FCB
= OPEN
I
OUT
= 20mA
3828 G26
V
OUT
20mV/DIV
I
L
0.5A/DIV
2µs/DIV
V
IN
= 12V
V
OUT
= 5V
V
FCB
= 5V
I
OUT
= 20mA
I
TH1
, I
TH2
(Pins 2, 13/Pins 30, 12): Error Amplifi er Output
and Switching Regulator Compensation Point. Each as-
sociated channels’ current comparator trip point increases
with this control voltage.
PHSMD (Pin 4, QFN Only): Control input to phase selector
which determines the phase relationship between control-
ler 1, controller 2 and the clockout signal.
V
OSENSE1
, V
OSENSE2
(Pins 5, 14/Pins 1, 13): Error Amplifi er
Feedback Input. Receives the remotely-sensed feedback
voltage for each controller from an external resistive divider
across the output.
PLLFLTR (Pin 6/Pin 2): Filter Connection for Phase-Locked
Loop. Alternatively, this pin can be driven with an AC or
DC voltage source to vary the frequency of the internal
oscillator.
FCB/PLLIN (Pin 8/Pin 5): Forced Continuous Control Input
and External Synchronization Input to Phase Detector. Pull-
ing this pin below 0.8V will force continuous synchronous
operation. Feeding an external clock signal will synchronize
the LTC3828 to the external clock.