Datasheet

LTC3828
21
3828fc
frequency f
O
. A voltage applied to the PLLFLTR pin of 1.2V
corresponds to a frequency of approximately 400kHz. The
nominal operating frequency range of the IC is 260kHz to
550kHz.
The phase detector used is an edge sensitive digital type
which provides zero degrees phase shift between the ex-
ternal and internal oscillators. This type of phase detector
will not lock up on input frequencies close to the harmonics
of the VCO center frequency. The PLL hold-in range, Δf
H
,
is equal to the capture range, Δf
C
:
Δf
H
= Δf
C
= ±0.5 f
O
(260kHz-550kHz)
The output of the phase detector is a complementary pair
of current sources charging or discharging the external
fi lter network on the PLLFLTR pin.
If the external frequency, f
PLLIN
, is greater than the oscillator
frequency, f
OSC
, current is sourced continuously, pulling
up the PLLFLTR pin. When the external frequency is less
than f
OSC
, current is sunk continuously, pulling down
the PLLFLTR pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. Thus the voltage on the PLLFLTR pin is
adjusted until the phase and frequency of the external and
internal oscillators are identical. At this stable operating
point the phase comparator output is open and the fi lter
capacitor C
LP
holds the voltage. The IC’s FCB/PLLIN pin
must be driven from a low impedance source such as a
logic gate located close to the pin. When using multiple
ICs for a phase-locked system, the PLLFLTR pin of the
master oscillator should be biased at a voltage that will
guarantee the slave oscillator(s) ability to lock onto the
master’s frequency. A DC voltage of 0.7V to 1.7V applied
to the master oscillator’s PLLFLTR pin is recommended
in order to meet this requirement. The resultant operating
frequency can range from 300kHz to 500kHz.
The loop fi lter components (C
LP
, R
LP
) smooth out the cur-
rent pulses from the phase detector and provide a stable
input to the voltage controlled oscillator. The fi lter compo-
nents C
LP
and R
LP
determine how fast the loop acquires
lock. Typically R
LP
=10k and C
LP
is 0.01µF to 0.1µF.
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time dura-
tion that each controller is capable of turning on the top
MOSFET. It is determined by internal timing delays and the
gate charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
Vf
ON MIN
OUT
IN
()
()
<
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for each controller is approximately
120ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases up to about 300ns.
This is of particular concern in forced continuous applica-
tions with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a signifi cant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
Voltage Positioning
Voltage positioning can be used to minimize peak-to-peak
output voltage excursions under worst-case transient
loading conditions. The open-loop DC gain of the control
loop is reduced depending upon the maximum load step
specifi cations. Voltage positioning can easily be added
to either or both controllers by loading the I
TH
pin with
a resistive divider having a Thevenin equivalent voltage
source equal to the midpoint operating voltage range of
the error amplifi er, or 1.2V (see Figure 10).
APPLICATIONS INFORMATION
I
TH
R
C
R
T1
INTV
CC
C
C
3828 F10
LTC3828
R
T2
Figure 10. Active Voltage Positioning Applied to the LTC3828