Datasheet

LTC3827-1
9
38271fe
FUNCTIONAL DIAGRAM
Main Control Loop
The LTC3827-1 uses a constant frequency, current mode
step-down architecture with the two controller channels
operating 180 degrees out of phase. During normal op-
eration, each external top MOSFET is turned on when the
clock for that channel sets the RS latch, and is turned off
when the main current comparator, I
CMP
, resets the RS
latch. The peak inductor current at which I
CMP
trips and
resets the latch is controlled by the voltage on the I
TH
pin,
which is the output of the error amplifi er EA. The error
amplifi er compares the output voltage feedback signal at
the V
FB
pin, (which is generated with an external resis-
tor divider connected across the output voltage, V
OUT
, to
ground) to the internal 0.800V reference voltage. When the
load current increases, it causes a slight decrease in V
FB
relative to the reference, which causes the EA to increase
the I
TH
voltage until the average inductor current matches
the new load current.
After the top MOSFET is turned off each cycle, the bottom
MOSFET is turned on until either the inductor current starts
to reverse, as indicated by the current comparator IR, or
the beginning of the next clock cycle.
(Refer to Functional Diagram)
SWITCH
LOGIC
+
–
4.7V
V
IN
V
IN
INTV
CC
-0.5V
0.8V
FC
BURSTEN
CLK2
CLK1
+
–
+
–
–
+
–
+
INTERNAL
SUPPLY
R
LP
C
LP
PLLIN/MODE
EXTV
CC
INTV
CC
SGND
+
5.25V/
7.5V
LDO
SW
SHDN
SLEEP
0.4V
TOP
BOOST
TG
C
B
C
IN
D
D
B
PGND
BOT
BG
INTV
CC
INTV
CC
V
IN
C
OUT
V
OUT
38271 FD
R
SENSE
R
B
V
FB
DROP
OUT
DET
FOLDBACK
BOT
TOP ON
S
R
Q
Q
OSCILLATOR
PHASE DET
PLLLPF
PLLIN/MODE
FC
BURSTEN
EA
0.88V
0.80V
TRACK/SS
OV
V
FB
0.5µA
1µA
6V
R
A
–
+
R
C
2(V
FB
)
RST
SHDN
TRACK/SS
1,13
2, 12
4, 10
3, 11
23, 18
25, 16
26, 15
24, 17
C
C
C
C2
C
SS
2(V
FB
)
0.45V
SLOPE
COMP
6mV
+
–
–
+
SENSE
–
SENSE
+
ICMP IR
B
RUN
8, 9
DUPLICATE FOR SECOND
CONTROLLER CHANNEL
+– –+
F
IN
+
–
+
–
PGOOD1
V
FB1
0.88V
0.72V
L
SHDN
6
5
27
22
20
19
7
28,14
21
I
TH
100k
OPERATION