Datasheet

LTC3827-1
11
38271fe
OPERATION
When the I
TH
voltage drops below 0.4V, the internal sleep
signal goes high (enabling “sleep” mode) and both external
MOSFETs are turned off. The I
TH
pin is then disconnected
from the output of the EA and “parked” at 0.425V.
In sleep mode, much of the internal circuitry is turned off,
reducing the quiescent current that the LTC3827-1 draws.
If one channel is shut down and the other channel is in
sleep mode, the LTC3827-1 draws only 80µA of quiescent
current. If both channels are in sleep mode, the LTC3827-1
draws only 115µA of quiescent current. In sleep mode,
the load current is supplied by the output capacitor. As
the output voltage decreases, the EA’s output begins to
rise. When the output voltage drops enough, the I
TH
pin
is reconnected to the output of the EA, the sleep signal
goes low, and the controller resumes normal operation
by turning on the top external MOSFET on the next cycle
of the internal oscillator.
When a controller is enabled for Burst Mode operation,
the inductor current is not allowed to reverse. The reverse
current comparator (IR) turns off the bottom external
MOSFET just before the inductor current reaches zero,
preventing it from reversing and going negative. Thus, the
controller operates in discontinuous operation.
In forced continuous operation, the inductor current is
allowed to reverse at light loads or under large transient
conditions. The peak inductor current is determined by
the voltage on the I
TH
pin, just as in normal operation.
In this mode, the effi ciency at light loads is lower than
in Burst Mode operation. However, continuous has the
advantages of lower output ripple and less interference
to audio circuitry. In forced continuous mode, the output
ripple is independent of load current.
When the PLLIN/MODE pin is connected for pulse-skipping
mode or clocked by an external clock source to use the
phase-locked loop (see Frequency Selection and Phase-
Locked Loop section), the LTC3827-1 operates in PWM
pulse-skipping mode at light loads. In this mode, constant
frequency operation is maintained down to approximately
1% of designed maximum output current. At very light
loads, the current comparator I
CMP
may remain tripped for
several cycles and force the external top MOSFET to stay
off for the same number of cycles (i.e., skipping pulses).
The inductor current is not allowed to reverse (discon-
tinuous operation). This mode, like forced continuous
operation, exhibits low output ripple as well as low audio
noise and reduced RF interference as compared to Burst
Mode operation. It provides higher low current effi ciency
than forced continuous mode, but not nearly as high as
Burst Mode operation.
Frequency Selection and Phase-Locked Loop (PLLLPF
and PLLIN/MODE Pins)
The selection of switching frequency is a tradeoff between
effi ciency and component size. Low frequency opera-
tion increases effi ciency by reducing MOSFET switching
losses, but requires larger inductance and/or capacitance
to maintain low output ripple voltage.
The switching frequency of the LTC3827-1’s controllers
can be selected using the PLLLPF pin.
If the PLLIN/MODE pin is not being driven by an external
clock source, the PLLLPF pin can be fl oated, tied to INTV
CC
,
or tied to SGND to select 400kHz, 530kHz, or 250kHz,
respectively.
A phase-locked loop (PLL) is available on the LTC3827-1
to synchronize the internal oscillator to an external clock
source that is connected to the PLLIN/MODE pin. In this
case, a series R-C should be connected between the
PLLLPF pin and SGND to serve as the PLL’s loop fi lter.
The LTC3827-1 phase detector adjusts the voltage on the
PLLLPF pin to align the turn-on of controller 1’s external
top MOSFET to the rising edge of the synchronizing signal.
Thus, the turn-on of controller 2’s external top MOSFET is
180 degrees out of phase to the rising edge of the external
clock source.
The typical capture range of the LTC3827-1’s phase-locked
loop is from approximately 115kHz to 800kHz, with a
guarantee over all manufacturing variations to be between
140kHz and 650kHz. In other words, the LTC3827-1’s PLL
is guaranteed to lock to an external clock source whose
frequency is between 140kHz and 650kHz.
The typical input clock thresholds on the PLLIN/MODE
pin are 1.6V (rising) and 1.2V (falling).
(Refer to Functional Diagram)