Datasheet

LTC3822-1
17
38221f
The selection of C
OUT
is driven by the effective series
resistance (ESR). Typically, once the ESR requirement
is satisfi ed, the capacitance is adequate for fi ltering. The
output ripple (ΔV
OUT
) is approximated by:
V I ESR
fC
OUT RIPPLE
OUT
≈+
⎛
⎝
⎜
⎞
⎠
⎟
•
••
1
8
where f is the operating frequency, C
OUT
is the output
capacitance and I
RIPPLE
is the ripple current in the induc-
tor. The output ripple is highest at maximum input voltage
since I
RIPPLE
increase with input voltage.
Topside MOSFET Drive Supply (C
B
, D
B
)
In the Functional Diagram, external bootstrap capaci-
tor C
B
is charged from a boost power source (usually
V
IN
) through diode D
B
when the SW node is low. When
a MOSFET is to be turned on, the C
B
voltage is applied
across the gate source of the desired device. When the
topside MOSFET is on, the BOOST pin voltage is above
the input supply. V
BOOST
= 2V
IN
. C
B
must be 100 times
the total input capacitance of the topside MOSFET. The
reverse breakdown of D
B
must be greater than V
IN(MAX)
.
Note that in applications where the supply voltage to C
B
exceeds V
IN
, the boost pin will draw approximately 500µA
in shutdown mode.
Setting Output Voltage
The LTC3822-1 output voltage is set by an external feed-
back resistor divider carefully placed across the output,
as shown in Figure 7. The regulated output voltage is
determined by:
VV
R
R
OUT
B
A
=+
⎛
⎝
⎜
⎞
⎠
⎟
06 1.•
For most applications, a 59k resistor is suggested for R
A
.
In applications where minimizing the quiescent current is
critical, R
A
should be made bigger to limit the feedback
divider current. If R
B
then results in very high impedance,
it may be benefi cial to bypass R
B
with a 10pF to 100pF
capacitor C
FF
.
Low Input Supply Voltage
Although the LTC3822-1 can function down to below
2.4V, the maximum allowable output current is reduced
as V
IN
decreases below 3V. Figure 8 shows the amount
of change as the supply is reduced down to 2.4V. Also
shown is the effect on V
REF
.
APPLICATIONS INFORMATION
Figure 8. Line Regulation of V
REF
and Maximum Sense Voltage
LTC3822-1
V
FB
V
OUT
R
B
C
FF
R
A
38221 F07
Figure 7. Setting the Output Voltage
INPUT VOLTAGE (V)
75
NORMALIZED VOLTAGE OR CURRENT (%)
85
95
105
80
90
100
2.2 2.4 2.6 2.8
38221 F08
3.02.12.0 2.3 2.5 2.7 2.9
V
REF
MAXIMUM
SENSE VOLTAGE
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest amount of
time that the LTC3822-1 is capable of turning the top
MOSFET on. It is determined by internal timing delays
and the gate charge required to turn on the top MOSFET.
Low duty cycle and high frequency applications may ap-
proach the minimum on-time limit and care should be
taken to ensure that:
t
V
fV
ON MIN
OUT
OSC IN
()
•
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