Datasheet

LTC3816
21
3816f
applicaTions inForMaTion
to lower the regulator output voltage. This current limit
condition persists until the fault condition disappears or
the controller detects a low output voltage fault and forces
the switcher output to latch off. Once the output voltage
is lower than the power good threshold, the controller
limits the maximum load to 1× to reduce the short-circuit
current.
A
CTIVE VOLTAGE POSITIONING (AVP)
In a conventional buck converter, the feedback control
regulates the output voltage to the same level for the
entire load range as shown in Figure 7a. The peak-to-peak
output voltage spikes resulting from the load step must
be smaller than the voltage tolerance window.
To reduce the regulator output voltage peak-to-peak
perturbation resulting from a load transient, the LTC3816
modulates the output voltage based on the output loading
current. The built-in AVP circuit lowers the output voltage
proportional
to
the load current as shown in Figure 7b.
Figure 7c shows the transient response with the AVP
function. The AVP voltage droop reduces the peak-to-peak
output voltage perturbation. As a result, the AVP topology
requires fewer capacitors at the regulator output to achieve
the same voltage tolerance window.
The AVP circuit obtains the load current information from
t
h
e sense resistor or the inductor DCR as shown in Figure 8.
The voltage drop across the sense resistor is extracted
Figure 7a. Transient Waveform Without AVP. The Transient
Peak-to-Peak Spike ≈ 130mV. The AITC Amplifier is
Configured as a Unity-Gain Amplifier
Figure 7b. AVP DC Transfer Curve
Figure 7c. Transient Waveform with AVP Slope = –3mV/A, Using
The Same Inductor and Output Capacitor as Figure 7a. The
Transient Peak-to-Peak Perturbation is Reduced to About 85mV
V
OUT
50mV/DIV
I
LOAD
10A/DIV
V
SW
20V/DIV
V
IN
= 12V
V
OUT
= 1V
I
LOAD
= 0A TO 20A
20µs/DIV
3816 F07a
I
LOAD
(A)
0
0.88
V
OUT
(V)
% FROM IDEAL NO-LOAD VALUE
0.91
0.94
0.97
1.00
1.03
–12
–9
–6
–3
0
3
5
10 15 20
3816 F07b
25 30
PROGRAMMABLE
AVP SLOPE
V
OUT
50mV/DIV
I
LOAD
10A/DIV
V
SW
20V/DIV
V
IN
= 12V
V
OUT
= 1V
I
LOAD
= 0A TO 20A
20µs/DIV
3816 F07c
by the AITC amplifier and summed with the differential
amplifier output voltage. The resulting output is servoed
to the VID DAC voltage. At higher load current, the volt-
age drop across the sense resistor increases, resulting
in a lower switcher output voltage. Typically, the system
requirement defines the amount of AVP gain ensuring
that the output voltage remains within the regulator sup-
ply tolerance band over the full range of load conditions.
Figure 8 includes the components required to compensate
for the sense resistor parasitic inductance. The AVP DC
transfer function is:
V
OUT
= V
DAC
– A
AVP(SR)
• I
L
= V
DAC
– A
G(SR)
• I
L
• R
SEN