Datasheet

LTC3816
16
3816f
Figure 2. LTC3816 Power-Up and Power-Down Timing Diagram
VR
ON
VID
DPRSLPVR
INTV
CC
45mV
V
CC(CORE)
V
BOOT
t
CLKEN#
IMVP-6
SLOW SLEW RATE
NORMAL
SLEW RATE
3816 F02
t
CLK(PWRGD)
CLKEN#
PWRGD
The LTC3816 is a constant frequency, voltage mode DC/DC
step-down controller that complies with the Intel IMVP-6/
IMVP-6.5 specifications. The 7-bit VID code programs the
switcher output voltage as specified in Table 1. Figure 2
shows the timing diagram. Upon start-up, the switcher
output soft-start ramps to the V
BOOT
voltage. 75µs after
reaching the V
BOOT
power good threshold, which is about
45mV below V
BOOT
, the controller forces the CLKEN# pin
low and the VID code is loaded. Next, the output is servoed
to its VID DAC potential. 10ms after regulation, PWRGD
pulls high to indicate that the switcher is regulating and
has completed its start-up phase.
The LTC3816 uses two external synchronous N-channel
MOSFETs. A floating topside driver and a simple external
charge pump provide full gate drive to the upper MOSFET.
The controller uses a leading edge modulation architec-
ture to allow extremely low duty cycles and fast load
step response. In a typical LTC3816 switching cycle, the
PWM comparator turns on the top MOSFET to charge the
output capacitor. An internal clock resets the top MOSFET
and turns on the bottom MOSFET to reduce the output
charging current. This switching cycle repeats itself at an
internally fixed frequency, or in synchronization with an
external oscillator.
The top gate duty cycle is controlled by the voltage feed-
back loop which includes an internal differential amplifier
that senses the differential output voltage between the
V
CC(SEN)
and V
SS(SEN)
pins. The AITC amplifier monitors
the inductor current and computes the load dependent
output droop required to implement the active voltage
positioning features in IMVP-6/IMVP-6.5. The IC servos
the differential output voltage to the VID DAC voltage
minus the small load dependent AVP droop.
The LTC3816 feedback loop is capable of dynamically
changing the regulator output to different VID DAC voltages.
Upon receiving a new VID code, the LTC3816 regulates to
its new potential with a programmable slew rate which is
selected to prevent the converter from generating audible
noise. The switcher output load current can be monitored
by measuring the I
MON
pin potential. The LTC3816 forces
the I
MON
pin voltage to be proportional to the average
load current with a gain configured by the R
PREIMON
and
R
IMON
resistors.
The LTC3816 includes an onboard current limit circuit that
senses the inductor current through an external sense
resistor or the inductor DCR. The peak inductor current
can be controlled by selecting the current limit R
IMAX
resistance. The LTC3816 current limit architecture allows
momentary overcurrent events for a predefined duration
(see the Current Sense and Current Limit sections). Upon
current limit, the top gate is shut off, the SS external
capacitor is discharged to limit the top gate duty cycle,
and the switcher output voltage is reduced until the load
fault is removed.
operaTion
(Refer to Funtional Diagram)