Datasheet
LTC3814-5
25
38145fc
To guarantee proper current limit at worst-case conditions,
increase nominal V
SNS
by 50% to 190mV. To check if the
current limit is acceptable at V
SNS
= 190mV, assume a
junction temperature of about 30°C above a 70°C ambient
(ρ
100°C
= 1.4):
I
IN(MAX)
≥
190mV
1.4 • 0.009Ω
−
1
2
•4A=13A
I
OUT(MAX)
= I
IN(MAX)
• (1-D
MAX
) = 6.5A
and double-check the assumed T
J
in the MOSFET:
P
TOP
=
1
1 0.5
6.5A
()
2
(1.4)(0.009)= 1.06W
T
J
= 70°C + 1.06W • 20°C/W = 91°C
Verify that the Si7848DP is also a good choice for the
bottom MOSFET by checking its power dissipation at
current limit and minimum input voltage, assuming a
junction temperature of 30°C above a 70°C ambient
(ρ
100°C
= 1.4):
P
BOT
= 0.5
6.5A
1 0.5
2
(1.4)(0.009)
+
1
2
(24V)
2
6.5A
1 0.5
(2)(400pF)
•
1
12V 3.5V
+
1
3.5V
(250kHz)
= 1.06W + 0.30W = 1.36W
T
J
= 70°C + 1.36W • 20°C/W = 97°C
The junction temperature will be signifi cantly less at
nominal current, but this analysis shows that careful at-
tention to heat sinking on the board will be necessary in
this circuit.
Since V
IN
is always between 4.5V and 14V, it can be con-
nected directly to the INTV
CC
and DRV
CC
pins.
C
OUT
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR
of 0.018Ω to minimize output voltage changes due to
inductor ripple current and load steps. The ripple voltage
will be only:
V
OUT(RIPPLE)
= (5A)
1
250kHz • 330μF
+
0.018
1 0.5
= 0.25V (about 1%)
A 0A to 5A load step will cause an output change of up to:
∆V
OUT(STEP)
= ∆I
LOAD
• ESR = 5A • 0.018Ω
= 90mV
An optional 10µF ceramic output capacitor is included
to minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 14.
APPLICATIONS INFORMATION