Datasheet

LTC3814-5
19
38145fc
Power Dissipation Considerations
Applications using large MOSFETs and high frequency
of operation may result in a large DRV
CC
/INTV
CC
supply
current. Therefore, when using the linear regulators, it is
necessary to verify that the resulting power dissipation
is within the maximum limits. The DRV
CC
/INTV
CC
supply
current consists of the MOSFET gate current plus the
LTC3814-5 quiescent current:
I
CC
= (f)(Q
G(TOP)
+ Q
G(BOTTOM)
) + 3mA
When using the internal LDO regulator, the power dissipa-
tion is internal so the rise in junction temperature can be
estimated from the equation given in Note 2 of the Electrical
Characteristics as follows:
T
J
= T
A
+ I
EXTVCC
• (V
EXTVCC
– V
INTVCC
)(38°C/W)
and must not exceed 125°C.
Likewise, if the external NMOS regulator is used, the worst
case power dissipation is calculated to be:
P
MOSFET
= (V
DRAIN(MAX)
– 5.5V) • I
CC
and can be used to properly size the device.
FEEDBACK LOOP/COMPENSATION
Introduction
In a typical LTC3814-5 circuit, the feedback loop consists of
two sections: the modulator/output stage and the feedback
amplifi er/compensation network. The modulator/output
stage consists of the current sense component and in-
ternal current comparator, the power MOSFET switches
and drivers, and the output fi lter and load. The transfer
function of the modulator/output stage for a boost con-
verter consists of an output capacitor pole, R
L
C
OUT
, and
an ESR zero, R
ESR
C
OUT
, and also a “right-half plane” zero,
(R
L
/L)(V
IN
2
/V
OUT
2
). It has a gain/phase curve that is typi-
cally like the curve shown in Figure 10 and is expressed
mathematically in the following equation.
H(s)=
V
OUT
(s)
V
ITH
(s)
=
R
L
•V
IN
•V
SENSE(MAX)
2.4 • V
OUT
•R
DS(ON)






•
1+ s•R
ESR
•C
OUT
1+ s•R
L
•C
OUT






•1 s•
L
R
L
•
V
OUT
2
V
IN
2






s = j2 f
This portion of the power supply is pretty well out of the
user’s control since the current sense is chosen based on
maximum output load, and the output capacitor is usually
chosen based on load regulation and ripple requirements
without considering AC loop response. The feedback am-
plifi er, on the other hand, gives us a handle on which to
adjust the AC response. The goal is to have an 180° phase
shift at DC so the loop regulates and less than 360° phase
shift at the point where the loop gain falls below 0dB, i.e.,
the crossover frequency, with as much gain as possible
at frequencies below the crossover frequency. Since the
feedback amplifi er adds an additional 90° phase shift to
the phase shift already present from the modulator/output
stage, some phase boost is required at the crossover
frequency to achieve good phase margin. The design
procedure (described in more detail in the next section) is
to (1) obtain a gain/phase plot of modulator/output stage,
(2) choose a crossover frequency and the required phase
boost, and (3) calculate the compensation network.
APPLICATIONS INFORMATION
Figure 10. Bode Plot of Boost Modulator/Output Stage
(1)
FREQUENCY (Hz)
GAIN (dB)
PHASE (DEG)
38145 F10
00
–90
–180
90
180
GAIN
PHASE