Datasheet

LTC3810
27
3810fc
Figure 14. Secondary Output Loop
where H(s) was given in Equation 2 and A(s) depends on
compensation circuit used:
Type 2:
A (s)=
1+ s•R2•C1
s•R1• C1+C2
()
•1+ s•R2•
C1• C2
C1+C2
⎛
⎝
⎜
⎞
⎠
⎟
Type 3:
A (s)=
1
s•R1• C1+C2
()
•
1+ s• R1+R3
()
•C3
()
•1+ s•R2•C1
()
1+ s•R3•C3
()
•1+ s•R2•
C1• C2
C1+C2
⎛
⎝
⎜
⎞
⎠
⎟
For SPICE, replace VSTIM line in the previous PSPICE
code with following code and generate a gain/phase plot
of V(out)/V(outin):
rfb1 outin vfb 52.5k
rfb2 vfb 0 10k
eithx ithx 0 laplace {0.8-v(vfb)} =
{1/(1+s/1000)}
eith ith 0 value={limit(1e6*v(ithx),0,2.4)}
cc1 ith vfb 4p
cc2 ith x1 8p
rc x1 vfb 210k
rf outin x2 11k ;delete this line for Type 2
cf x2 vfb 120p ;delete this line for Type 2
vstim out outin dc=0 ac=1m
Pulse Skip Mode Operation and MODE/SYNC Pin
The MODE/SYNC pin determines whether the bottom
MOSFET remains on when current reverses in the inductor.
Tying this pin above its 0.8V threshold enables pulse skip
mode operation where the bottom MOSFET turns off when
inductor current reverses. The load current at which current
reverses and discontinuous operation begins depends on
the amplitude of the inductor ripple current and will vary
with changes in V
IN
. Tying the MODE/SYNC pin below the
0.8V threshold forces continuous synchronous operation,
allowing current to reverse at light loads and maintain-
ing high frequency operation. To prevent forcing current
back into the main power supply, potentially boosting the
input supply to a dangerous voltage level, forced continu-
ous mode of operation is disabled when the TRACK/SS
voltage is below the reference voltage during soft-start
or tracking. During these two periods, the PGOOD signal
is forced low.
In addition to providing a logic input to force continu-
ous operation, the MODE/SYNC pin provides a mean to
maintain a fl yback winding output when the primary is
operating in pulse skip mode. The secondary output V
OUT2
is normally set as shown in Figure 14 by the turns ratio
N of the transformer. However, if the controller goes into
pulse skip mode and halts switching due to a light primary
load current, then V
OUT2
will droop. An external resistor
divider from V
OUT2
to the MODE/SYNC pin sets a minimum
APPLICATIONS INFORMATION
V
IN
LTC3810
SGND
FCB
TG
SW
R3
R4
3810 F14
T1
1:N
BG
PGND
+
C
OUT2
1μF
V
OUT1
V
OUT2
V
IN
+
C
IN
1N4148
•
•
+
C
OUT