Datasheet

LTC3809
16
3809fc
For most applications, a 59k resistor is suggested for R
A
.
In applications where minimizing the quiescent current is
critical, R
A
should be made bigger to limit the feedback
divider current. If R
B
then results in ver y high impedance,
it may be benefi cial to bypass R
B
with a 50pF to 100pF
capacitor C
FF
.
Run and Soft-Start Functions
The LTC3809 has a low power shutdown mode which is
controlled by the RUN pin. Pulling the RUN pin below 1.1V
puts the LTC3809 into a low quiescent current shutdown
mode (I
Q
= 9μA). Releasing the RUN pin, an internal 0.7μA
(at V
IN
= 4.2V) current source will pull the RUN pin up
to V
IN
, which enables the controller. The RUN pin can be
driven directly from logic as showed in Figure 4.
Once the controller is enabled, the start-up of V
OUT
is
controlled by the internal soft-start, which slowly ramps
the positive reference to the error amplifi e r f r o m 0 V t o 0 . 6 V,
allowing V
OUT
to rise smoothly from 0V to its fi nal value.
The default internal soft-start time is around 1ms.
is an edge sensi tive digi tal t ype that pr ov ides zero de grees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complementary
current sources that charge or discharge the external fi lter
network connected to the PLLLPF pin. The relationship
between the voltage on the PLLLPF pin and operating
frequency, when there is a clock signal applied to SYNC/
MODE, is shown in Figure 5 and specifi ed in the electrical
characteristics table. Note that the LTC3809 can only be
synchronized to an external clock whose frequency is within
range of the LTC3809’s internal VCO, which is nominally
200kHz to 1MHz. This is guaranteed, over temperature and
process variations, to be between 250kHz and 750kHz. A
simplifi ed block diagram is shown in Figure 6.
APPLICATIONS INFORMATION
LTC3809
V
FB
V
OUT
R
B
C
FF
R
A
3809 F03
Figure 3. Settling Output Voltage
3.3V OR 5V
3809 F04
LTC3809
RUN
LTC3809
RUN
Figure 4. RUN Pin Interfacing
Phase-Locked Loop and Frequency Synchronization
The LTC3809 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the external P-channel
M O S F E T t o b e l o c k e d t o t h e r i s i n g e d g e o f a n e x t e r n a l c l o c k
signal applied to the SYNC/MODE pin. The phase detector
PLLLPF PIN VOLTAGE (V)
0.2
0
FREQUENCY (kHz)
0.7 1.2 1.7
3809 F05
2.2
200
400
600
800
1000
1200
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3809 F06
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
MODE
Figure 5. Relationship Between Oscillator Frequency
and Voltage at the PLLLPF Pin When Synchronizing to
an External Clock
Figure 6. Phase-Locked Loop Block Diagram