Datasheet

LTC3789
24
3789fa
applicaTions inForMaTion
The Vishay SiR422DP has a typical R
DS(ON)
of 0.010Ω at
T
J
= 125°C and V
GS
= 4.5V.
The maximum dissipation in QB occurs at maximum input
voltage when the circuit is operating in the buck region.
The dissipation is:
P
B,BUCK
=
V
IN
− V
OUT
V
IN
• I
OUT(MAX)
2
• ρ
τ
• R
DS(ON)
R
DS(ON)
(125°C) <
1.3W
18V TO −12V
18V
• (5A)
2
= 0.156Ω
This seems to indicate that a quite small MOSFET can be
used for QB if we only look at power loss. However, with
5A current the voltage drop across 0.156Ω is 0.78V, which
means the MOSFET body diode is conducting. To avoid
body diode current flow we should keep the maximum
voltage drop well below 0.5V, using, for example, Vishay
Si4840BDY in the SO-8 package (R
DSON(MAX)
= 0.012Ω).
Select QC and QD. With 12V output voltage we need
MOSFETs with 20V or higher rating.
The highest dissipation occurs at minimum input voltage
when the inductor current is highest. For switch QC the
dissipation is:
P
C,BOOST
=
(V
OUT
− V
IN
)V
OUT
V
IN
2
• I
OUT(MAX)
2
• ρ
τ
• R
DS(ON)
+ k • V
OUT
3
•
I
OUT(MAX)
V
IN
• C
RSS
• f
where C
RSS
is usually specified by the MOSFET manufac-
turers. The constant k, which accounts for the loss caused
by reverse recovery current, is inversely proportional to
the gate drive current and has an empirical value of 1.7.
The dissipation in switch QD is:
P
D,BOOST
=
V
IN
V
OUT
•
V
OUT
V
IN
• I
OUT(MAX)






2
• ρ
τ
• R
DS(ON)
Vishay SiR484OY is a possible choice for QC and QD. The
calculated power loss at 5V input voltage is then 1.3W for
QC and 0.84W for QD.
C
IN
is chosen to filter the square current in the buck region.
In this mode, the maximum input current peak is:
I
IN,PEAK(MAX,BUCK)
= 5A • 1+
29%
2






= 5.7A
A low ESR (10mΩ) capacitor is selected. Input voltage
ripple is 57mV (assuming ESR dominates the ripple).
C
OUT
is chosen to filter the square current in the boost
region. In this mode, the maximum output current peak is:
I
OUT,PEAK(MAX,BOOST)
=
12
5
• 5 • 1+
11%
2






= 10.6A
A low ESR (5mΩ) capacitor is suggested. This capacitor
will limit output voltage ripple to 53mV (assuming ESR
dominates the ripple).
PC Board Layout Checklist
The basic PC board layout requires a dedicated ground
plane layer. Also, for high current, a multilayer board
provides heat sinking for power components.
• The ground plane layer should not have any traces and
should be as close as possible to the layer with power
MOSFETs.
• Place C
IN
, switch A, switch B and D1 in one com-
pact area. Place C
OUT
, switch C, switch D and D2 in
one compact area. One layout example is shown in
Figure 12.
• Use immediate vias to connect the components (in-
cluding the LTC3789’s SGND and PGND pins) to the
ground plane. Use several large vias for each power
component.