Datasheet

LTC3789
18
3789fa
applicaTions inForMaTion
clock whose frequency is within range of the LTC3789’s
internal VCO. This is guaranteed to be between 200kHz
and 600kHz. A simplified block diagram is shown in
Figure 10.
For a given ripple the inductance terms in continuous
mode are as follows:
L
BOOST
>
V
IN(MIN)
2
•(V
OUT
– V
IN(MIN)
) • 100
f • I
OUT(MAX)
• %Ripple • V
OUT2
H,
L
BUCK
>
V
OUT
• V
IN(MAX)
– V
OUT
(
)
• 100
f • I
OUT(MAX)
• %Ripple • V
IN(MAX)
H
where:
f is operating frequency, Hz
% Ripple is allowable inductor current ripple
V
IN(MIN)
is minimum input voltage, V
V
IN(MAX)
is maximum input voltage, V
V
OUT
is output voltage, V
I
OUT(MAX)
is maximum output load current, A
For high efficiency, choose an inductor with low core
loss, such as ferrite. Also, the inductor should have low
DC resistance to reduce the I
2
R losses, and must be able
to handle the peak inductor current without saturating. To
minimize radiated noise, use a toroid, pot core or shielded
bobbin inductor.
C
IN
and C
OUT
Selection
In the boost region, input current is continuous. In the
buck region, input current is discontinuous. In the buck
region, the selection of input capacitor C
IN
is driven by
the need to filter the input square wave current. Use a low
ESR capacitor sized to handle the maximum RMS current.
For buck operation, the input RMS current is given by:
I
RMS
≈ I
OUT(MAX)
•
V
OUT
V
IN
•
V
IN
V
OUT
– 1
This formula has a maximum at V
IN
= 2V
OUT
, where
I
RMS
= I
OUT(MAX)
/2. This simple worst-case condition
is commonly used for design because even significant
deviations do not offer much relief. Note that ripple cur-
rent ratings from capacitor manufacturers are often based
on only 2000 hours of life which makes it advisable to
derate the capacitor.
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.4V
10µA
5V
R
SET
3789 F10
FREQ
SYNC
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 10. Phase-Locked Loop Block Diagram
If the external clock frequency is greater than the inter-
nal oscillator’s frequency, f
OSC
, then current is sourced
continuously from the phase detector output, pulling up
the filter network. When the external clock frequency is
less than f
OSC
, current is sunk continuously, pulling down
the filter network. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for the amount of time corresponding to
the phase difference. The voltage on the filter network is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the filter capacitor holds the voltage.
Typically, the external clock (on the MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thresh-
old is 1V.
Inductor Selection
The operating frequency and inductor selection are inter-
related in that higher operating frequencies allow the use
of smaller inductor and capacitor values. The inductor
value has a direct effect on ripple current. The inductor
current ripple ∆I
L
is typically set to 20% to 40% of the
maximum inductor current in the boost region at V
IN(MIN)
.