Datasheet

LTC3788-1
21
37881fc
APPLICATIONS INFORMATION
Minimum On-Time Considerations
Minimum on-time, t
ON(MIN)
, is the smallest time duration
that the LTC3788-1 is capable of turning on the bottom
MOSFET. It is determined by internal timing delays and
the gate charge required to turn on the top MOSFET. Low
duty cycle applications may approach this minimum on-
time limit.
In forced continuous mode, if the duty cycle falls below
what can be accommodated by the minimum on-time,
the controller will begin to skip cycles but the output will
continue to be regulated. More cycles will be skipped when
V
IN
increases. Once V
IN
rises above V
OUT
, the loop works
to keep the top MOSFET on continuously. The minimum
on-time for the LTC3788-1 is approximately 110ns.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the greatest improvement. Percent efficiency
can be expressed as:
%Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc., are the individual losses as a percent-
age of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3788-1 circuits: 1) IC V
IN
current, 2) IN-
TV
CC
regulator current, 3) I
2
R losses, 4) Bottom MOSFET
transition losses.
1. The V
IN
current is the DC supply current given in the
Electrical Characteristics table, which excludes MOSFET
driver and control currents. V
IN
current typically results
in a small (<0.1%) loss.
2. INTV
CC
current is the sum of the MOSFET driver and
control currents. The MOSFET driver current results
from switching the gate capacitance of the power MOS-
FETs. Each time a MOSFET gate is switched from low to
high to low again, a packet of charge, dQ, moves from
INTV
CC
to ground. The resulting dQ/dt is a current out
of INTV
CC
that is typically much larger than the control
circuit current. In continuous mode, I
GATECHG
= f(Q
T
+
Q
B
), where Q
T
and Q
B
are the gate charges of the topside
and bottom side MOSFETs.
3. DC I
2
R losses. These arise from the resistances of the
MOSFETs, sensing resistor, inductor and PC board traces
and cause the efficiency to drop at high output currents.
4. Transition losses apply only to the bottom MOSFET(s),
and become significant only when operating at low input
voltages (typically 15V or greater). Transition losses can
be estimated from:
Transition Loss = (1.7)
V
OUT
3
V
IN
I
O(MAX)
•C
RSS
f
Other hidden losses, such as copper trace and internal
battery resistances, can account for an additional 5% to
10% efficiency degradation in portable systems. It is very
important to include these system-level losses during the
design phase.
Checking Transient Response
The regulator loop response can be checked by looking at
the load current transient response. Switching regulators
take several cycles to respond to a step in DC (resistive)
load current. When a load step occurs, V
OUT
shifts by an
amount equal to ∆I
LOAD
(ESR), where ESR is the effective
series resistance of C
OUT
. ∆I
LOAD
also begins to charge
or discharge C
OUT
generating the feedback error signal
that forces the regulator to adapt to the current change and
return V
OUT
to its steady-state value. During this recov-
ery time V
OUT
can be monitored for excessive overshoot
or ringing, which would indicate a stability problem.
OPTI-LOOP compensation allows the transient response
to be optimized over a wide range of output capacitance
and ESR values. The availability of the ITH pin not only
allows optimization of control loop behavior, but it also
provides a DC coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/
or damping factor can be estimated using the percentage
of overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin. The I
TH
external components shown in Figure 9 circuit will provide
an adequate starting point for most applications.