Datasheet

LTC3788-1
20
37881fc
APPLICATIONS INFORMATION
Fault Conditions: Overtemperature Protection
At higher temperatures, or in cases where the internal
power dissipation causes excessive self-heating on chip
(such as an INTV
CC
short to ground), the overtemperature
shutdown circuitry will shut down the LTC3788-1. When
the junction temperature exceeds approximately 170°C,
the overtemperature circuitry disables the INTV
CC
LDO,
causing the INTV
CC
supply to collapse and effectively shut
down the entire LTC3788-1 chip. Once the junction tem-
perature drops back to approximately 155°C, the INTV
CC
LDO turns back on. Long term overstress (T
J
> 125°C)
should be avoided as it can degrade the performance or
shorten the life of the part.
Phase-Locked Loop and Frequency Synchronization
The LTC3788-1 has an internal phase-locked loop (PLL)
comprised of a phase frequency detector, a low pass filter
and a voltage-controlled oscillator (VCO). This allows the
turn-on of the top MOSFET of controller 1 to be locked to
the rising edge of an external clock signal applied to the
PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET
is thus 180 degrees out-of-phase with the external clock.
The phase detector is an edge-sensitive digital type that
provides zero degrees phase shift between the external
and internal oscillators. This type of phase detector does
not exhibit false lock to harmonics of the external clock.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced continu-
ously from the phase detector output, pulling up the VCO
input. When the external clock frequency is less than f
OSC
,
current is sunk continuously, pulling down the VCO input.
If the external and internal frequencies are the same but
exhibit a phase difference, the current sources turn on for
an amount of time corresponding to the phase difference.
The voltage at the VCO input is adjusted until the phase
and frequency of the internal and external oscillators are
identical. At the stable operating point, the phase detector
output is high impedance and the internal filter capacitor,
C
LP
, holds the voltage at the VCO input.
Typically, the external clock (on PLLIN/MODE pin) input
high threshold is 1.6V, while the input low threshold is 1.2V.
Note that the LTC3788-1 can only be synchronized to an
external clock whose frequency is within range of the
LTC3788-1’s internal VCO, which is nominally 55kHz to
1MHz. This is guaranteed to be between 75kHz and 850kHz.
Rapid phase locking can be achieved by using the FREQ pin
to set a free-running frequency near the desired synchro-
nization frequency. The VCO’s input voltage is prebiased
at a frequency corresponding to the frequency set by the
FREQ pin. Once prebiased, the PLL only needs to adjust
the frequency slightly to achieve phase lock and synchro-
nization. Although it is not required that the free-running
frequency be near external clock frequency, doing so will
prevent the operating frequency from passing through a
large range of frequencies as the PLL locks.
Table 1 summarizes the different states in which the FREQ
pin can be used.
Table 1.
FREQ PIN PLLIN/MODE PIN FREQUENCY
0V DC Voltage 350kHz
INTV
CC
DC Voltage 535kHz
Resistor DC Voltage 50kHz to 900kHz
Any of the Above External Clock Phase Locked to
External Clock
Figure 6. Relationship Between Oscillator
Frequency and Resistor Value at the FREQ Pin
FREQ PIN RESISTOR (k)
15
FREQUENCY (kHz)
600
800
1000
35 45 5525
37881 F06
400
200
500
700
900
300
100
0
65 75 85 95 105 115
125