Datasheet

LTC3787
26
3787fc
A 6.8H inductor will produce a 31% ripple current. The
peak inductor current will be the maximum DC value plus
one half the ripple current, or 9.25A.
The R
SENSE
resistor value can be calculated by using the
maximum current sense voltage specification with some
accommodation for tolerances:
R
SENSE
≤
75mV
9.25A
= 0.008Ω
Choosing 1% resistors: R
A
= 5k and R
B
= 95.3k yields an
output voltage of 24.072V.
The power dissipation on the top side MOSFET in each chan-
nel can be easily estimated. Choosing a Vishay Si7848BDP
MOSFET results in: R
DS(ON)
= 0.012, C
MILLER
= 150pF.
At maximum input voltage with T (estimated) = 50°C:
P
MAIN
=
(24V – 12V) 24V
(12V)
2
•(4A)
2
•1+(0.005)(50°C–25°C)
⎡
⎣
⎤
⎦
• 0.008Ω
+ (1.7)(24V)
3
4A
12V
(150pF)(350kHz)=0.7W
C
OUT
is chosen to filter the square current in the output.
The maximum output current peak is:
I
OUT(PEAK)
= 8• 1+
31%
2
⎛
⎝
⎜
⎞
⎠
⎟
= 9.3A
A low ESR (5m) capacitor is suggested. This capacitor
will limit output voltage ripple to 46.5mV (assuming ESR
dominate ripple).
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the IC. These items are also illustrated graphically in the
layout diagram of Figure 8. Figure 9 illustrates the current
waveforms present in the various branches of the 2-phase
synchronous regulators operating in the continuous mode.
Check the following in your layout:
1. Put the bottom N-channel MOSFETs MBOT1 and MBOT2
and the top N-channel MOSFETs MTOP1 and MTOP2
in one compact area with C
OUT
.
2. Are the signal and power grounds kept separate? The
combined IC signal ground pin and the ground return of
C
INTVCC
must return to the combined C
OUT
(–) terminals.
The path formed by the bottom N-channel MOSFET
and the capacitor should have short leads and PC trace
lengths. The output capacitor (–) terminals should be
connected as close as possible to the source terminals
of the bottom MOSFETs.
3. Does the LTC3787 VFB pin’s resistive divider connect to
the (+) terminal of C
OUT
? The resistive divider must be
connected between the (+) terminal of C
OUT
and signal
ground and placed close to the VFB pin. The feedback
resistor connections should not be along the high cur-
rent input feeds from the input capacitor(s).
4. Are the SENSE
–
and SENSE
+
leads routed together with
minimum PC trace spacing? The filter capacitor between
SENSE
+
and SENSE
–
should be as close as possible
to the IC. Ensure accurate current sensing with Kelvin
connections at the sense resistor.
5. Is the INTV
CC
decoupling capacitor connected close
to the IC, between the INTV
CC
and the power ground
pins? This capacitor carries the MOSFET drivers’ cur-
rent peaks. An additional 1F ceramic capacitor placed
immediately next to the INTV
CC
and PGND pins can help
improve noise performance substantially.
6. Keep the switching nodes (SW1, SW2), top gate nodes
(TG1, TG2) and boost nodes (BOOST1, BOOST2) away
from sensitive small-signal nodes, especially from
the opposites channel’s voltage and current sensing
feedback pins. All of these nodes have very large and
fast moving signals and, therefore, should be kept on
the output side of the LTC3787 and occupy a minimal
PC trace area.
7. Use a modified “star ground” technique: a low imped-
ance, large copper area central grounding point on
the same side of the PC board as the input and output
capacitors with tie-ins for the bottom of the INTV
CC
decoupling capacitor, the bottom of the voltage feedback
resistive divider and the SGND pin of the IC.
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