Datasheet

21
LTC3778
3778f
Figure 10. 1.25V/±6A Sink and Source at 550kHz
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16
15
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12
11
1
2
3
4
6
7
8
9
10
RUN/SS
V
ON
PGOOD
V
RNG
I
TH
FCB
SGND
I
ON
V
FB
EXTV
CC
BOOST
TG
SW
SENSE
+
SENSE
–
PGND
BG
DRV
CC
INTV
CC
V
IN
LTC3778
+
M2
IRF7811
M1
IRF7811
L1, 1.8µH
D1
B340A
C
OUT1-2
180µF
4V
×2
C
OUT3
22µF
6.3V
X7R
C
IN
10µF
35V
×3
V
IN
5V TO 25V
V
OUT
1.25V
±6A
C
SS
0.1µF
C
C1
1500pF
C
ON
, 0.01µF
C
C2
100pF
C
VCC
4.7µF
C
F
0.1µF
C
B
0.22µF
R
C
20k
R1
12.7k
R
ON
227k
R2
11.7k
R
F
1Ω
D
B
CMDSH-3
3778 F11
C
IN
: UNITED CHEMICON THCR60EIHI06ZT
C
OUT1-2
: CORNELL DUBILIER ESRE181E04B
L1: SUMIDA CEP125-1R8MC-H
R
PG
100k
330µF
25V,
SANYO
ELECTROLYTIC
+
R2
68Ω
R1
1.2k
5
• Segregate the signal and power grounds. All small
signal components should return to the SGND pin at
one point which is then tied to the PGND pin close to the
source of M2.
• Place M2 as close to the controller as possible, keeping
the PGND, BG and SW traces short.
• Connect the input capacitor(s) C
IN
close to the power
MOSFETs. This capacitor carries the MOSFET AC cur-
rent.
• Keep the high dV/dT SW, BOOST and TG nodes away
from sensitive small-signal nodes.
• Connect the INTV
CC
decoupling capacitor C
VCC
closely
to the INTV
CC
and PGND pins.
• Connect the top driver boost capacitor C
B
closely to the
BOOST and SW pins.
• Connect the V
IN
pin decoupling capacitor C
F
closely to
the V
IN
and PGND pins.
APPLICATIO S I FOR ATIO
WUUU
Figure 10 shows a DDR memory termination application in
which the output can sink and source up to 6A of current.
The resistive divider of R1 and R2 are meant to introduce
TYPICAL APPLICATIO S
U
an offset to the SENSE
–
pin so that the current limit is
symmetrical during both sink and source.