Datasheet

17
LTC3778
3778f
APPLICATIO S I FOR ATIO
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During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components shown in Figure 7
will provide adequate compensation for most applica-
tions. For a detailed explanation of switching control loop
theory see Linear Technology Application Note 76.
Design Example
As a design example, take a supply with the following
specifications: V
IN
= 7V to 28V (15V nominal), V
OUT
= 2.5V
±5%, I
OUT(MAX)
= 10A, f = 250kHz. First, calculate the
timing resistor with V
ON
= V
OUT
:
R
kHz pF
k
ON
=
()()
=
1
250 10
400 Ω
and choose the inductor for about 40% ripple current at
the maximum V
IN
:
L
V
kHz A
V
V
H=
()()()
−






=µ
25
250 0 4 10
1
25
28
23
.
.
.
.
Selecting a standard value of 1.8µH results in a maximum
ripple current of:
∆=
()
µ
()






=I
V
kHz H
V
V
A
L
25
250 1 8
1
25
28
51
.
.
–
.
.
Next, choose the synchronous MOSFET switch. Choosing
a Si4874 (R
DS(ON)
= 0.0083Ω (NOM) 0.010Ω (MAX),
θ
JA
= 40°C/W) yields a nominal sense voltage of:
V
SNS(NOM)
= (10A)(1.3)(0.0083Ω) = 108mV
Tying V
RNG
to 1.1V will set the current sense voltage range
for a nominal value of 110mV with current limit occurring
at 146mV. To check if the current limit is acceptable,
assume a junction temperature of about 80°C above a
70°C ambient with ρ
150°C
= 1.5:
I
mV
AA
LIMIT
≥
()
Ω
()
+
()
=
146
15 0010
1
2
51 12
..
.
and double check the assumed T
J
in the MOSFET:
P
VV
V
AW
BOT
=
()()
Ω
()
=
28 2 5
28
12 15 0010 197
2
–.
.. .
T
J
= 70°C + (1.97W)(40°C/W) = 149°C
Because the top MOSFET is on for such a short time, an
Si4884 R
DS(ON)(MAX)
= 0.0165Ω, C
RSS
= 100pF will be
sufficient. Checking its power dissipation at current limit
with ρ
100°C
= 1.4:
P
V
V
A
VApFkHz
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TOP
=
()()
Ω
()
+
()( )( )( )( )
=+=
25
28
12 1 4 0 0165
1 7 28 12 100 250
030 040 07
2
2
.
..
.
...
T
J
= 70°C + (0.7W)(40°C/W) = 98°C
The junction temperatures will be significantly less at
nominal current, but this analysis shows that careful
attention to heat sinking will be necessary in this circuit.
C
IN
is chosen for an RMS current rating of about 5A at
85°C. The output capacitors are chosen for a low ESR of
0.013Ω to minimize output voltage changes due to induc-
tor ripple current and load steps. The ripple voltage will be
only:
∆V
OUT(RIPPLE)
= ∆I
L(MAX)
(ESR)
= (5.1A) (0.013Ω) = 66mV
However, a 0A to 10A load step will cause an output
change of up to:
∆V
OUT(STEP)
= ∆I
LOAD
(ESR) = (10A) (0.013Ω) = 130mV
An optional 22µF ceramic output capacitor is included to
minimize the effect of ESL in the output ripple. The
complete circuit is shown in Figure 7.