Datasheet

19
LTC3776
3776fa
frequency, when there is a clock signal applied to SYNC/
SSEN, is shown in Figure 9 and specified in the Electrical
Characteristics table. Note that the LTC3776 can only be
synchronized to an external clock whose frequency is
within range of the LTC3776’s internal VCO, which is
nominally 200kHz to 1MHz. This is guaranteed, over
temperature and process variations, to be between 250kHz
and 850kHz. A simplified block diagram is shown in
Figure 10.
If the external clock frequency is greater than the internal
oscillator’s frequency, f
OSC
, then current is sourced con-
tinuously from the phase detector output, pulling up the
PLLLPF pin. When the external clock frequency is less
than f
OSC
, current is sunk continuously, pulling down the
PLLLPF pin. If the external and internal frequencies are the
same but exhibit a phase difference, the current sources
turn on for an amount of time corresponding to the phase
difference. The voltage on the PLLLPF pin is adjusted until
the phase and frequency of the internal and external
APPLICATIO S I FOR ATIO
WUUU
PLLLPF PIN VOLTAGE (V)
0
0
FREQUENCY (kHz)
0.5 1 1.5 2
3776 F09
2.4
200
400
600
800
1000
1200
1400
Figure 9. Relationship Between Oscillator Frequency and Voltage
at the PLLLPF Pin When Synchronizing to an External Clock
DIGITAL
PHASE/
FREQUENCY
DETECTOR
OSCILLATOR
2.4V
R
LP
C
LP
3776 F10
PLLLPF
EXTERNAL
OSCILLATOR
SYNC/
SSEN
Figure 10. Phase-Locked Loop Block Diagram
oscillators are identical. At the stable operating point, the
phase detector output is high impedance and the filter
capacitor C
LP
holds the voltage.
The loop filter components, C
LP
and R
LP
, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The filter
components C
LP
and R
LP
determine how fast the loop
acquires lock. Typically R
LP
= 10k and C
LP
is 2200pF to
0.01μF.
Typically, the external clock (on SYNC/SSEN pin) input high
threshold is 1.6V, while the input low threshold is 1.2V.
Table 2 summarizes the different states in which the
PLLLPF pin can be used.
Table 2
PLLLPF PIN SYNC/SSEN PIN FREQUENCY
0V GND 300kHz
Floating GND 550kHz
V
IN
GND 750kHz
RC Loop Filter Clock Signal Phase-Locked to External Clock
Capacitor to V
IN
Spread Spectrum Operation
GND 450kHz to 550kHz
Low Supply Operation
Although the LTC3776 can function down to below 2.4V,
the maximum allowable output current is reduced as V
IN
decreases below 3V. Figure 11 shows the amount of
change as the supply is reduced down to 2.4V. Also shown
is the effect on V
REF
.
INPUT VOLTAGE (V)
75
NORMALIZED VOLTAGE OR CURRENT (%)
85
95
105
80
90
100
2.2 2.4 2.6 2.8
3776 F11
3.02.12.0 2.3 2.5 2.7 2.9
V
REF
MAXIMUM
SENSE VOLTAGE
Figure 11. Line Regulation of V
REF
and
Maximum Sense Voltage for Low Input Supply