Datasheet

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LTC3776

3776fa

, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst

Mode is a registered trademark of Linear Technology Corporation. No R

SENSE

is a

trademark of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents including 5481178, 5929620, 6144194,

6580258, 6304066, 6611131, 6498466, patent pending on Spread Spectrum.

Dual 2-Phase, No R

SENSE

Synchronous Controller for

DDR/QDR Memory Termination

High Efficiency, 2-Phase, DDR Memory (V

DDQ

and V

) Supplies

■

No Current Sense Resistors Required

■

Out-of-Phase Controllers Reduce Required

Input Capacitance

■

OUT2

Tracks 1/2 V

REF

■

Symmetrical Source/Sink Output Current

Capability (V

OUT2

)

■

Spread Spectrum Operation (When Enabled)

■

Wide V

Range: 2.75V to 9.8V

■

Constant Frequency Current Mode Operation

■

0.6V ±1.5% Voltage Reference (V

OUT1

)

■

Low Dropout Operation: 100% Duty Cycle

■

True PLL for Frequency Locking or Adjustment

■

Internal Soft-Start Circuitry

■

Power Good Output Voltage Monitor

■

Output Overvoltage Protection

■

Micropower Shutdown: I

= 9μA

■

Tiny Low Profile (4mm × 4mm) QFN and Narrow

SSOP Packages

The LTC

3776 is a 2-phase dual output synchronous step-

down switching regulator controller for DDR/QDR memory

termination applications. The second controller regulates

its output voltage to 1/2 V

REF

while providing symmetrical

source and sink output current capability.

The No R

SENSE

constant frequency current mode architec-

ture eliminates the need for sense resistors and improves

efficiency. Power loss and noise due to the ESR of the

input capacitance are minimized by operating the two

controllers out of phase.

The switching frequency can be programmed up to 750kHz,

allowing the use of small surface mount inductors and ca-

pacitors. For noise sensitive applications, the LTC3776

switching frequency can be externally synchronized from

250kHz to 850kHz, or can be enabled for spread spectrum

operation. Forced continuous operation reduces noise and

RF interference. Soft-start for V

OUT1

is provided internally

and can be extended using an external capacitor.

The LTC3776 is available in the tiny thermally enhanced

(4mm × 4mm) QFN package or 24-lead SSOP narrow

package.

■

DDR, DDR II and QDR Memory

■

SSTL, HSTL Termination Supplies

■

Servers, RAID Systems

■

Distributed DC Power Systems

SENSE1

LTC3776

SGND

SENSE2

TG1 TG2

SW1 SW2

BG1 BG2

PGND PGND

REF

FB2

470pF

DDQ

OUT1

2.5V

OUT2

)

1.25V

±4A

47μF

15k

2200pF

6.2k

59k

187k

1.5μH

TH1

3776 TA01a

TH2

10μF

×2

3.3V

FB1

LOAD CURRENT (mA)

EFFICIENCY (%)

100

10 100 1000 10000

3776 TA01b

FIGURE 14 CIRCUIT

CHANNEL 2 (V

= 3.3V)

CHANNEL 1 (V

= 5V)

CHANNEL 1 (V

= 3.3V)

CHANNEL 2 (V

= 5V)

Efficiency vs Load Current

FEATURES

DESCRIPTIO

APPLICATIO S

TYPICAL APPLICATIO

Summary of content (28 pages)

PAGE 1
LTC3776 Dual 2-Phase, No RSENSETM, Synchronous Controller for DDR/QDR Memory Termination U FEATURES DESCRIPTIO ■ The LTC®3776 is a 2-phase dual output synchronous stepdown switching regulator controller for DDR/QDR memory termination applications. The second controller regulates its output voltage to 1/2 VREF while providing symmetrical source and sink output current capability.
PAGE 2
LTC3776 W W W AXI U U ABSOLUTE RATI GS (Note 1) Input Supply Voltage (VIN) ........................ – 0.3V to 10V PLLLPF, RUN/SS, SYNC/SSEN, VREF, SENSE1+, SENSE2+, VFB2 IPRG1, IPRG2 Voltages ................. – 0.3V to (VIN + 0.3V) VFB1, ITH1, ITH2 Voltages ........................... – 0.3V to 2.4V SW1, SW2 Voltages .............. –2V to VIN + 1V (10V Max) PGOOD ..................................................... – 0.3V to 10V TG1, TG2, BG1, BG2 Peak Output Current (<10μs) .....
PAGE 3
LTC3776 ELECTRICAL CHARACTERISTICS The ● denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 4.2V unless otherwise specified. PARAMETER CONDITIONS MIN Output Voltage Load Regulation ITH = 0.9V (Note 5) ITH = 1.7V VFB1 Input Current (Note 5) Overvoltage Protect Threshold Measured at VFB with Respect to Regulated Feedback Voltage 10 Overvoltage Protect Hysteresis TYP MAX UNITS 0.12 –0.12 0.5 –0.5 % % 10 50 nA 13.
PAGE 4
LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS TA = 25°C unless otherwise noted. Step from Sinking to Sourcing Load Current (CH2) Efficiency vs Load Current 100 90 VOUT2 100mV/DIV AC-COUPLED 80 EFFICIENCY (%) 70 60 50 LOAD CURRENT 500mA/DIV 40 30 FIGURE 14 CIRCUIT CHANNEL 2 (VIN = 3.3V) CHANNEL 1 (VIN = 5V) CHANNEL 1 (VIN = 3.3V) CHANNEL 2 (VIN = 5V) 20 10 0 10 100 1000 LOAD CURRENT (mA) 20μs/DIV VIN = 3.
PAGE 5
LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS Regulated Feedback Voltage (CH2) vs Temperature Maximum Current Sense Voltage vs ITH2 Pin Voltage (CH2) 1.2625 80 1.2600 Regulated Feedback Voltage (CH1) vs Temperature 0.612 VREF = 2.500V FEEDBACK VOLTAGE (VFB1) (V) FEEDBACK VOLTAGE (VFB2) (V) 100 1.2575 60 CURRENT LIMIT (%) TA = 25°C unless otherwise noted. 1.2550 40 1.2525 20 1.2500 0 1.2475 –20 1.2450 –40 1.2425 –60 –100 0 2.0 1.5 1.0 ITH2 VOLTAGE (V) 1.
PAGE 6
LTC3776 U W TYPICAL PERFOR A CE CHARACTERISTICS Shutdown Quiescent Current vs Input Voltage SHUTDOWN CURRENT (μA) RUN/SS Start-Up Current vs Input Voltage 0.9 RUN/SS = 0V RUN/SS PIN PULL-UP CURRENT (μA) 20 18 16 14 12 10 8 6 4 2 0 2 3 4 8 6 5 7 INPUT VOLTAGE (V) 9 10 3736 G17 U U U PI FU CTIO S TA = 25°C unless otherwise noted. RUN/SS = 0V 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.
PAGE 7
LTC3776 U U U PI FU CTIO S (UF/GN Package) using the phase-locked loop, apply a CMOS compatible clock with a frequency between 250kHz and 850kHz to this pin. Tie this pin to GND to enable constant frequency operation (300kHz, 550kHz or 750kHz as determined by the state of the PLLLPF pin). Tie this pin to VIN to enable spread spectrum operation. In spread spectrum mode, the LTC3776’s frequency is randomly varied between 450kHz and 580kHz.
PAGE 8
LTC3776 W FU CTIO AL DIAGRA U (Controller 1) U VIN SENSE1+ CIN RS1 CLK1 S TG1 MP1 Q R SWITCHING LOGIC AND BLANKING CIRCUIT OV1 SC1 PGND SW1 ANTISHOOT THROUGH L1 VOUT1 SENSE1+ COUT1 BG1 MN1 PGND SLOPE1 SW1 – ICMP SENSE1+ + IPROG1 SHDN – + VFB1 R1B EAMP + R1A – 0.6V ITH1 EXTSS INTSS RITH1 + OV1 VFB1 SC1 OVP – 0.68V + 0.
PAGE 9
LTC3776 W FU CTIO AL DIAGRA U (Controller 2) U SENSE2+ RS2 CLK2 TG2 MP2 Q S VIN R SWITCHING LOGIC AND BLANKING CIRCUIT OV2 SC2 PGND SW2 ANTISHOOT THROUGH L2 SENSE2+ VOUT2 COUT2 BG2 MN2 PGND SLOPE2 SW2 – ICMP SENSE2+ SHDN + VFB2 – + 40k EAMP + VREF 40k – 120k 40k ITH2 RITH2 + OV2 VFB2 SC2 OVP – VREF/8 – VFB2/2 CITH2 SCP 1.
PAGE 10
LTC3776 U OPERATIO (Refer to Functional Diagram) When the load current increases, it causes a slight decrease in VFB relative to the reference, which in turn causes the ITH voltage to increase until the average inductor current matches the new load current. While the top P-channel MOSFET is off, the bottom N-channel MOSFET is turned on until the beginning of the next cycle. Shutdown, Soft-Start and Tracking Start-Up (RUN/SS and TRACK Pins) The LTC3776 is shut down by pulling the RUN/SS pin low.
PAGE 11
LTC3776 U OPERATIO (Refer to Functional Diagram) phase detector adjusts the voltage on the PLLLPF pin to align the turn-on of controller 1’s external P-channel MOSFET to the rising edge of the synchronizing signal. Thus, the turn-on of controller 2’s external P-channel MOSFET is 180 degrees out of phase with the rising edge of the external clock source.
PAGE 12
LTC3776 (Refer to Functional Diagram) output noise spectrum of a conventional buck switching converter (1/2 of LTC3776 with spread spectrum operation disabled) with VIN = 5V, VOUT = 2.5V and IOUT = 2A. Unlike conventional buck converters, the LTC3776’s internal oscillator can be selected to produce a clock pulse whose frequency is randomly varied between 450kHz and 580kHz by tying the SYNC/SSEN pin to VIN.
PAGE 13
LTC3776 U OPERATIO (Refer to Functional Diagram) The peak inductor current is determined by the peak sense voltage and the on-resistance of the external P-channel MOSFET: IPK = ΔVSENSE(MAX) RDS(ON) Power Good (PGOOD) Pin A window comparator monitors both feedback voltages and the open-drain PGOOD output pin is pulled low when either or both feedback voltages are not within ±10% of their reference voltages. PGOOD is low when the LTC3776 is shut down or in undervoltage lockout.
PAGE 14
LTC3776 U W U U APPLICATIO S I FOR ATIO inductor current is limited by the current threshold, set by the voltage on the ITH pin of the current comparator. The voltage on the ITH pin is internally clamped, which limits the maximum current sense threshold ΔVSENSE(MAX). 2.0 INPUT CAPACITOR RMS CURRENT 1.8 SINGLE PHASE DUAL CONTROLLER 1.6 1.4 2-PHASE DUAL CONTROLLER 1.2 1.0 The output current that the LTC3776 can provide is given by: 0.8 0.6 0.4 IOUT(MAX) = VOUT1 = 2.5V/2A VOUT2 = 1.8V/2A 0.
PAGE 15
LTC3776 U W U U APPLICATIO S I FOR ATIO Reasonable starting criteria for selecting the P-channel MOSFET are that it must typically have a gate charge (QG) less than 25nC to 30nC (at 4.5VGS) and a turn-off delay (tD(OFF)) of less than approximately 140ns.
PAGE 16
LTC3776 U W U U APPLICATIO S I FOR ATIO Operating Frequency and Synchronization The choice of operating frequency, fOSC, is a trade-off between efficiency and component size. Low frequency operation improves efficiency by reducing MOSFET switching losses, both gate charge loss and transition loss. However, lower frequency operation requires more inductance for a given amount of ripple current.
PAGE 17
LTC3776 U W U U APPLICATIO S I FOR ATIO size for most LTC3776 applications, since it conducts a relatively small average current. Larger diodes result in additional transition losses due to their larger junction capacitance. This diode may be omitted if the efficiency loss can be tolerated. CIN and COUT Selection The selection of CIN is simplified by the 2-phase architecture and its impact on the worst-case RMS current drawn through the input network (battery/fuse/capacitor).
PAGE 18
LTC3776 U W U U APPLICATIO S I FOR ATIO Channel 2’s output voltage is set to 1/2 VREF by connecting the VFB2 pin to VOUT2. To improve the frequency response, a feed-forward capacitor, CFF, may be used. Great care should be taken to route the VFB line away from noise sources, such as the inductor or the SW line. VOUT1 CFF VOUT2 RB tSS1 = CSS • LTC3776 VFB1 During soft-start, the start-up of VOUT1 is controlled by slowly ramping the positive reference to the error amplifier from 0V to 0.
PAGE 19
LTC3776 U W U U APPLICATIO S I FOR ATIO frequency, when there is a clock signal applied to SYNC/ SSEN, is shown in Figure 9 and specified in the Electrical Characteristics table. Note that the LTC3776 can only be synchronized to an external clock whose frequency is within range of the LTC3776’s internal VCO, which is nominally 200kHz to 1MHz. This is guaranteed, over temperature and process variations, to be between 250kHz and 850kHz. A simplified block diagram is shown in Figure 10.
PAGE 20
LTC3776 U W U U APPLICATIO S I FOR ATIO Minimum On-Time Considerations Minimum on-time, tON(MIN), is the smallest amount of time in which the LTC3776 is capable of turning the top P-channel MOSFET on and then off. It is determined by internal timing delays and the gate charge required to turn on the top MOSFET.
PAGE 21
LTC3776 U W U U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3776. These items are illustrated in the layout diagram of Figure 12. Figure 13 depicts the current waveforms present in the various branches of the 2-phase dual regulator.
PAGE 22
LTC3776 U W U U APPLICATIO S I FOR ATIO MP1 L1 VOUT1 COUT1 MN1 + RL1 VIN RIN CIN + MP2 BOLD LINES INDICATE HIGH, SWITCHING CURRENT LINES. KEEP LINES TO A MINIMUM LENGTH L2 MN2 VOUT2 COUT2 + RL2 3776 F13 Figure 13.
PAGE 23
LTC3776 U TYPICAL APPLICATIO S RFB1A 59k RFB1B 187k CITH1A 100pF VIN 5V CIN 10μF ×2 22 23 24 1 2 3 4 SW1 SENSE1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS RITH1 CITH1 22k 1000pF RVIN 10Ω CITH2 CVIN 2.2nF 1μF RITH2 6.2k CSS 10nF CITH2B 330pF + 21 L1 1.5μH MP1 20 19 18 17 16 15 MN1 Si7540DP VDDQ 2.5V 5A COUT1 100μF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 SW2 VREF PGND COUT2 100μF MN2 Si7540DP MP2 L2 1.5μH VTT 1.
PAGE 24
LTC3776 U TYPICAL APPLICATIO S RFB1A 59k RFB1B 187k CITH1A 100pF VIN 3.3V 22 23 24 1 2 3 4 SW1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS RITH1 CITH1 22k 1000pF RVIN 10Ω CIN 22μF CITH2 CVIN 2.2nF 1μF RITH2 6.2k CSS 10nF CITH2A 330pF 21 SENSE1+ L1 2.2μH MP1 FDC638P 20 19 18 17 16 15 MN1 FDC637N VDDQ 2.5V 2A COUT1 47μF 14 13 BG2 9 12 PGND PGOOD 7 11 SENSE2+ VFB2 8 ITH2 10 6 VREF SW2 PGND COUT2 47μF MN2 FDC637N MP2 FDC638P L2 2.2μH VTT 1.
PAGE 25
LTC3776 U TYPICAL APPLICATIO S CFF1 100pF CITH1 220pF CLP 10nF VIN 3.3V RFB1B 187k RITH1 15k RLP 15k RVIN 10Ω CIN 22μF CITH2 CVIN 220pF 1μF RITH2 15k CLK IN 1 2 3 4 5 6 7 + 24 SW1 SENSE1 IPRG1 PGND BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF TG2 SGND LTC3776EGN 5 VIN RUN/SS MP1 23 22 21 20 19 18 SW1 L1 1.5μH MN1 Si7540DP D1 MN2 Si7540DP D2 VDDQ 2.5V 4A + COUT1 150μF 17 16 BG2 12 15 PGND PGOOD 10 14 SENSE2+ VFB2 11 ITH2 13 9 VREF SW2 MP2 SW2 + RFB1A 59k L2 1.
PAGE 26
LTC3776 U PACKAGE DESCRIPTIO UF Package 24-Lead Plastic QFN (4mm × 4mm) (Reference LTC DWG # 05-08-1697) 0.70 ±0.05 4.50 ± 0.05 2.45 ± 0.05 3.10 ± 0.05 (4 SIDES) PACKAGE OUTLINE 0.25 ±0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS 4.00 ± 0.10 (4 SIDES) BOTTOM VIEW—EXPOSED PAD 0.75 ± 0.05 R = 0.115 TYP PIN 1 NOTCH R = 0.20 TYP OR 0.35 × 45° CHAMFER 23 24 0.40 ± 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 2.45 ± 0.10 (4-SIDES) (UF24) QFN 0105 0.200 REF 0.00 – 0.05 0.25 ± 0.05 0.50 BSC NOTE: 1.
PAGE 27
LTC3776 U PACKAGE DESCRIPTIO GN Package 24-Lead Plastic SSOP (Narrow .150 Inch) (Reference LTC DWG # 05-08-1641) .337 – .344* (8.560 – 8.738) 24 23 22 21 20 19 18 17 16 15 1413 .033 (0.838) REF .045 ±.005 .229 – .244 (5.817 – 6.198) .254 MIN .150 – .157** (3.810 – 3.988) .150 – .165 1 .0165 ± .0015 2 3 4 5 6 7 8 9 10 11 12 .0250 BSC RECOMMENDED SOLDER PAD LAYOUT .015 ± .004 × 45° (0.38 ± 0.10) .0075 – .0098 (0.19 – 0.25) .0532 – .0688 (1.35 – 1.75) .004 – .0098 (0.102 – 0.
PAGE 28
LTC3776 U TYPICAL APPLICATIO 2-Phase, Spread Spectrum, DDR Memory Supplies with Ceramic Output Capacitors RFB1A 59k RFB1B 187k CITH1A 100pF CITH1 1000pF RITH1 22k 2200pF VIN 3.3V RVIN 10Ω CIN 22μF CITH2 CVIN 2.2nF 1μF RITH2 6.2k 22 23 24 1 2 3 4 21 SENSE1+ SW1 PGND IPRG1 BG1 VFB1 ITH1 SYNC/SSEN TG1 IPRG2 PGND PLLLPF SGND TG2 LTC3776EUF 5 VIN RUN/SS 20 19 18 17 16 15 MN1 FDC637N VDDQ 2.