Datasheet

LTC3775
4
3775fa
ELECTRICAL CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating
junction temperature range, otherwise specifi cations are at T
A
= 25°C (Note 2). V
IN
= 12V, V
RUN
= 5V, unless otherwise specifi ed.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Oscillator
f
OSC
Oscillator Frequency R
SET
= 39.2k
l
425 500 575 kHz
f
HIGH
Maximum Oscillator Frequency
l
1000 kHz
f
LOW
Minimum Oscillator Frequency
l
250 kHz
f
SYNC
External Sync Frequency Range With Reference to Free Running –20 20 %
t
ON(MIN)
TG Minimum On-Time (Notes 6, 8) V
MODE/SYNC
= 0V 30 ns
t
OFF(MIN)
TG Minimum Off-Time (Note 6) 300 ns
DC
MAX
Maximum TG Duty Cycle f
OSC
= 500kHz
l
90 %
V
MODE
MODE/SYNC Threshold MODE/SYNC Rising 1.2 V
V
MODE(HYST)
MODE/SYNC Hysteresis 430 mV
R
MODE/SYNC
MODE/SYNC Input Resistance to SGND 50 k
Driver
BG R
UP
Bottom Gate (BG) Pull-Up On-Resistance 2.5 
TG R
UP
Top Gate (TG) Pull-Up On-Resistance 2.5 
BG R
DOWN
Bottom Gate (BG) Pull-Down On-Resistance 1.0 
TG R
DOWN
Top Gate (TG) Pull-Down On-Resistance 1.5 
BG, TG t
2D
Bottom Gate Off to Top Gate On Delay
Top Switch-On Delay Time
C
L
= 3300pF (Note 7) 15 ns
TG, BG t
1D
Top Gate Off to Bottom Gate On Delay
Synchronous Switch-On Delay Time
C
L
= 3300pF (Note 7) 15 ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3775 is tested under pulsed load conditions such that T
J
≈ T
A
.
The LTC3775E is guaranteed to meet specifi cations from 0°C to 85°C
junction temperature. Specifi cations over the –40°C to 125°C operating
junction temperature range are assured by design, characterization and
correlation with statistical process controls. The LTC3775I is guaranteed
over the –40°C to 125°C operating junction temperature range. Note that
the maximum ambient temperature consistent with these specifi cations
is determined by specifi c operating conditions in conjunction with board
layout, the rated package thermal impedance and other environmental
factors.
The junction temperature (T
J
, in °C) is calculated from the ambient
temperature (T
A
, in °C) and power dissipation (P
D
, in Watts) according to
the formula:
T
J
= T
A
+ (P
D
• θ
JA
), where θ
JA
(in °C/W) is the package thermal
impedance.
Note 3: Failure to solder the exposed pad of the UD package to the PC
board will result in a thermal resistance much higher than 68°C/W.
Note 4: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specifi ed.
Note 5: Supply current in normal operation is dominated by the current
needed to charge and discharge the external MOSFET gates. This current
will vary with supply voltage and the external MOSFETs used.
Note 6: Guaranteed by design, not subject to test.
Note 7: Rise and fall times are measured using 10% and 90% levels. Delay
and nonoverlap times are measured using 50% levels.
Note 8: The LTC3775 leading edge modulation architecture does not have
a minimum TG pulse width requirement. The TG minimum pulse width is
limited by the SW node rise and fall times.