Datasheet

LTC3775
20
3775fa
INTV
CC
when the switch node is low. When the top MOSFET
turns on, the switch node rises to V
IN
and the BOOST pin
rises to approximately V
IN
+ INTV
CC
. The boost capacitor
needs to store at least 100 times the gate charge required
by the top MOSFET. In most applications a 0.1µF to 1µF
X5R or X7R dielectric capacitor is adequate. The reverse
breakdown of the Schottky diode, D
B
, must be greater
than V
IN(MAX)
.
Power MOSFET Selection
The LTC3775 requires two external N-channel power
MOSFETs, one for the top (main) switch and one for the
bottom (synchronous) switch. Important parameters for
the power MOSFETs are the threshold voltage V
(GS)TH
,
breakdown voltage V
(BR)DSS
, maximum current I
DS(MAX)
,
on-resistance R
DS(ON)
and input capacitance.
The gate drive voltage is set by the 5.2V INTV
CC
supply.
Consequently, logic-level threshold MOSFETs must be
used in LTC3775 applications. If the INTV
CC
voltage is
expected to drop below 5V, then sub-logic level threshold
MOSFETs should be considered. Pay close attention to the
V
(BR)DSS
specifi cation because most logic-level MOSFETs
are limited to 30V or less. The MOSFETs selected should
have a V
(BR)DSS
rating greater than the maximum input
voltage and some margin should be added for transients
and spikes.
MOSFET input capacitance is a combination of several
components but can be taken from the typical “gate charge”
curve included on most data sheets (Figure 15). The curve
is generated by forcing a constant input current into the
gate of a common source, current source loaded stage
and then plotting the gate voltage versus time. The initial
slope is the effect of the gate-to-source and the gate-
to-drain capacitance. The fl at portion of the curve is the
result of the Miller multiplication effect of the drain-to-gate
capacitance as the drain voltage drops. The upper sloping
line is due to the drain-to-gate accumulation capacitance
and the gate-to-source capacitance. The Miller charge (the
increase in coulombs on the horizontal axis from a to b
while the curve is fl at) is specifi ed for a given V
DS
drain
voltage, but can be adjusted for different V
DS
voltages by
multiplying by the ratio of the application V
DS
to the curve
specifi ed V
DS
values. To estimate the capacitance C
MILLER
,
take the change in gate charge from points a and b on a
manufacturer’s data sheet and divide by the stated V
DS
voltage specifi ed. C
MILLER
is the most important selec-
tion criteria for determining the transition loss term in
the top MOSFET but is not directly specifi ed on MOSFET
data sheets. C
RSS
and C
OS
are specifi ed sometimes but
defi nitions of these parameters are not included.
When the controller is operating in continuous mode the
duty cycles for the top and bottom MOSFETs are given
by:
Top Gate Duty Cycle =
V
OUT
V
IN
Bottom Gate Duty Cycle =
V
IN
–V
OUT
V
IN






The power dissipation for the top and bottom MOSFETs
at maximum output current are given by:
P
TOP
=
V
OUT
V
IN
I
OUT MAX)
2
()
(T(TOP)
()
R
DS(ON)(MAX)
()
+V
IN
2
I
OUT(MAX)
2
R
DR
()
C
MILLER
()
•
1
INTV
CC
–V
TH(IL)
+
1
V
TH(IL)
•f
SW
P
BOT
=
V
IN
–V
OUT
V
IN
I
OUT( AX)
2
()
MT(TOP)
()
R
DS(ON)(MAX)
()
where:
R
DR
= Effective top driver resistance
V
TH(IL)
= MOSFET data sheet specifi ed typical gate
threshold voltage at the specifi ed drain current
APPLICATIONS INFORMATION
+
–
V
DS
V
IN
V
GS
MILLER EFFECT
Q
IN
ab
C
MILLER
= (Q
B
– Q
A
)/V
DS
V
GS
V
+
–
3775 F15
Figure 15. Gate Charge Characteristics